From cefe3d0b19d4f3fdbd72bd171ad411e906b76b23 Mon Sep 17 00:00:00 2001 From: Martin Wehking Date: Fri, 17 Jul 2026 16:47:16 +0000 Subject: [PATCH 1/2] Use FMOV instead of INS. For some intrinsics, the actualy AArch64 instruction that is lowered to is FMOV instead of INS. Also, the registers the arg prep maps to can be more precisely labeled as Xn. Before, the generic 'rn' notation was used, but since the AArch64 Instruction column contains A64 specific assembly, we can map it to 64 bit GPRs directly to avoid confusion. Remove also some duplicates. --- neon_intrinsics/advsimd.md | 12 ++++-------- tools/intrinsic_db/advsimd.csv | 12 ++++-------- 2 files changed, 8 insertions(+), 16 deletions(-) diff --git a/neon_intrinsics/advsimd.md b/neon_intrinsics/advsimd.md index 3b602956..ead91a46 100644 --- a/neon_intrinsics/advsimd.md +++ b/neon_intrinsics/advsimd.md @@ -2631,10 +2631,6 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. | float64x2_t vreinterpretq_f64_p128(poly128_t a) | `a -> Vd.1Q` | `NOP` | `Vd.2D -> result` | `A64` | | poly64x2_t vreinterpretq_p64_p128(poly128_t a) | `a -> Vd.1Q` | `NOP` | `Vd.2D -> result` | `A32/A64` | | float16x8_t vreinterpretq_f16_p128(poly128_t a) | `a -> Vd.1Q` | `NOP` | `Vd.8H -> result` | `A32/A64` | -| mfloat8x8_t vreinterpret_mf8_u8(uint8x8_t a) | `a -> Vd.8B` | `NOP` | `Vd.8B -> result` | `A64` | -| mfloat8x16_t vreinterpretq_mf8_u8(uint8x16_t a) | `a -> Vd.16B` | `NOP` | `Vd.16B -> result` | `A64` | -| uint8x8_t vreinterpret_u8_mf8(mfloat8x8_t a) | `a -> Vd.8B` | `NOP` | `Vd.8B -> result` | `A64` | -| uint8x16_t vreinterpretq_u8_mf8(mfloat8x16_t a) | `a -> Vd.16B` | `NOP` | `Vd.16B -> result` | `A64` | ### Move @@ -3261,7 +3257,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. | int16x8_t vdupq_n_s16(int16_t value) | `value -> rn` | `DUP Vd.8H,rn` | `Vd.8H -> result` | `v7/A32/A64` | | int32x2_t vdup_n_s32(int32_t value) | `value -> rn` | `DUP Vd.2S,rn` | `Vd.2S -> result` | `v7/A32/A64` | | int32x4_t vdupq_n_s32(int32_t value) | `value -> rn` | `DUP Vd.4S,rn` | `Vd.4S -> result` | `v7/A32/A64` | -| int64x1_t vdup_n_s64(int64_t value) | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `v7/A32/A64` | +| int64x1_t vdup_n_s64(int64_t value) | `value -> Xn` | `FMOV Dd,Xn` | `Vd.1D -> result` | `v7/A32/A64` | | int64x2_t vdupq_n_s64(int64_t value) | `value -> rn` | `DUP Vd.2D,rn` | `Vd.2D -> result` | `v7/A32/A64` | | uint8x8_t vdup_n_u8(uint8_t value) | `value -> rn` | `DUP Vd.8B,rn` | `Vd.8B -> result` | `v7/A32/A64` | | uint8x16_t vdupq_n_u8(uint8_t value) | `value -> rn` | `DUP Vd.16B,rn` | `Vd.16B -> result` | `v7/A32/A64` | @@ -3269,9 +3265,9 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. | uint16x8_t vdupq_n_u16(uint16_t value) | `value -> rn` | `DUP Vd.8H,rn` | `Vd.8H -> result` | `v7/A32/A64` | | uint32x2_t vdup_n_u32(uint32_t value) | `value -> rn` | `DUP Vd.2S,rn` | `Vd.2S -> result` | `v7/A32/A64` | | uint32x4_t vdupq_n_u32(uint32_t value) | `value -> rn` | `DUP Vd.4S,rn` | `Vd.4S -> result` | `v7/A32/A64` | -| uint64x1_t vdup_n_u64(uint64_t value) | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `v7/A32/A64` | +| uint64x1_t vdup_n_u64(uint64_t value) | `value -> Xn` | `FMOV Dd,Xn` | `Vd.1D -> result` | `v7/A32/A64` | | uint64x2_t vdupq_n_u64(uint64_t value) | `value -> rn` | `DUP Vd.2D,rn` | `Vd.2D -> result` | `v7/A32/A64` | -| poly64x1_t vdup_n_p64(poly64_t value) | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `A32/A64` | +| poly64x1_t vdup_n_p64(poly64_t value) | `value -> Xn` | `FMOV Dd,Xn` | `Vd.1D -> result` | `A32/A64` | | poly64x2_t vdupq_n_p64(poly64_t value) | `value -> rn` | `DUP Vd.2D,rn` | `Vd.2D -> result` | `A32/A64` | | float32x2_t vdup_n_f32(float32_t value) | `value -> rn` | `DUP Vd.2S,rn` | `Vd.2S -> result` | `v7/A32/A64` | | float32x4_t vdupq_n_f32(float32_t value) | `value -> rn` | `DUP Vd.4S,rn` | `Vd.4S -> result` | `v7/A32/A64` | @@ -3279,7 +3275,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. | poly8x16_t vdupq_n_p8(poly8_t value) | `value -> rn` | `DUP Vd.16B,rn` | `Vd.16B -> result` | `v7/A32/A64` | | poly16x4_t vdup_n_p16(poly16_t value) | `value -> rn` | `DUP Vd.4H,rn` | `Vd.4H -> result` | `v7/A32/A64` | | poly16x8_t vdupq_n_p16(poly16_t value) | `value -> rn` | `DUP Vd.8H,rn` | `Vd.8H -> result` | `v7/A32/A64` | -| float64x1_t vdup_n_f64(float64_t value) | `value -> rn` | `INS Dd.D[0],xn` | `Vd.1D -> result` | `A64` | +| float64x1_t vdup_n_f64(float64_t value) | `value -> Xn` | `FMOV Dd,Xn` | `Vd.1D -> result` | `A64` | | float64x2_t vdupq_n_f64(float64_t value) | `value -> rn` | `DUP Vd.2D,rn` | `Vd.2D -> result` | `A64` | | mfloat8x8_t vdup_n_mf8(mfloat8_t value) | `value -> rn` | `DUP Vd.8B,rn` | `Vd.8B -> result` | `A64` | | mfloat8x16_t vdupq_n_mf8(mfloat8_t value) | `value -> rn` | `DUP Vd.16B,rn` | `Vd.16B -> result` | `A64` | diff --git a/tools/intrinsic_db/advsimd.csv b/tools/intrinsic_db/advsimd.csv index 10e53a6b..0f490039 100644 --- a/tools/intrinsic_db/advsimd.csv +++ b/tools/intrinsic_db/advsimd.csv @@ -1925,7 +1925,7 @@ int16x4_t vdup_n_s16(int16_t value) value -> rn DUP Vd.4H,rn Vd.4H -> result v7/ int16x8_t vdupq_n_s16(int16_t value) value -> rn DUP Vd.8H,rn Vd.8H -> result v7/A32/A64 int32x2_t vdup_n_s32(int32_t value) value -> rn DUP Vd.2S,rn Vd.2S -> result v7/A32/A64 int32x4_t vdupq_n_s32(int32_t value) value -> rn DUP Vd.4S,rn Vd.4S -> result v7/A32/A64 -int64x1_t vdup_n_s64(int64_t value) value -> rn INS Dd.D[0],xn Vd.1D -> result v7/A32/A64 +int64x1_t vdup_n_s64(int64_t value) value -> Xn FMOV Dd,Xn Vd.1D -> result v7/A32/A64 int64x2_t vdupq_n_s64(int64_t value) value -> rn DUP Vd.2D,rn Vd.2D -> result v7/A32/A64 uint8x8_t vdup_n_u8(uint8_t value) value -> rn DUP Vd.8B,rn Vd.8B -> result v7/A32/A64 uint8x16_t vdupq_n_u8(uint8_t value) value -> rn DUP Vd.16B,rn Vd.16B -> result v7/A32/A64 @@ -1933,9 +1933,9 @@ uint16x4_t vdup_n_u16(uint16_t value) value -> rn DUP Vd.4H,rn Vd.4H -> result v uint16x8_t vdupq_n_u16(uint16_t value) value -> rn DUP Vd.8H,rn Vd.8H -> result v7/A32/A64 uint32x2_t vdup_n_u32(uint32_t value) value -> rn DUP Vd.2S,rn Vd.2S -> result v7/A32/A64 uint32x4_t vdupq_n_u32(uint32_t value) value -> rn DUP Vd.4S,rn Vd.4S -> result v7/A32/A64 -uint64x1_t vdup_n_u64(uint64_t value) value -> rn INS Dd.D[0],xn Vd.1D -> result v7/A32/A64 +uint64x1_t vdup_n_u64(uint64_t value) value -> Xn FMOV Dd,Xn Vd.1D -> result v7/A32/A64 uint64x2_t vdupq_n_u64(uint64_t value) value -> rn DUP Vd.2D,rn Vd.2D -> result v7/A32/A64 -poly64x1_t vdup_n_p64(poly64_t value) value -> rn INS Dd.D[0],xn Vd.1D -> result A32/A64 +poly64x1_t vdup_n_p64(poly64_t value) value -> Xn FMOV Dd,Xn Vd.1D -> result A32/A64 poly64x2_t vdupq_n_p64(poly64_t value) value -> rn DUP Vd.2D,rn Vd.2D -> result A32/A64 float32x2_t vdup_n_f32(float32_t value) value -> rn DUP Vd.2S,rn Vd.2S -> result v7/A32/A64 float32x4_t vdupq_n_f32(float32_t value) value -> rn DUP Vd.4S,rn Vd.4S -> result v7/A32/A64 @@ -1943,7 +1943,7 @@ poly8x8_t vdup_n_p8(poly8_t value) value -> rn DUP Vd.8B,rn Vd.8B -> result v7/A poly8x16_t vdupq_n_p8(poly8_t value) value -> rn DUP Vd.16B,rn Vd.16B -> result v7/A32/A64 poly16x4_t vdup_n_p16(poly16_t value) value -> rn DUP Vd.4H,rn Vd.4H -> result v7/A32/A64 poly16x8_t vdupq_n_p16(poly16_t value) value -> rn DUP Vd.8H,rn Vd.8H -> result v7/A32/A64 -float64x1_t vdup_n_f64(float64_t value) value -> rn INS Dd.D[0],xn Vd.1D -> result A64 +float64x1_t vdup_n_f64(float64_t value) value -> Xn FMOV Dd,Xn Vd.1D -> result A64 float64x2_t vdupq_n_f64(float64_t value) value -> rn DUP Vd.2D,rn Vd.2D -> result A64 mfloat8x8_t vdup_n_mf8(mfloat8_t value) value -> rn DUP Vd.8B,rn Vd.8B -> result A64 mfloat8x16_t vdupq_n_mf8(mfloat8_t value) value -> rn DUP Vd.16B,rn Vd.16B -> result A64 @@ -3942,10 +3942,6 @@ int64x2_t vreinterpretq_s64_p128(poly128_t a) a -> Vd.1Q NOP Vd.2D -> result A32 float64x2_t vreinterpretq_f64_p128(poly128_t a) a -> Vd.1Q NOP Vd.2D -> result A64 poly64x2_t vreinterpretq_p64_p128(poly128_t a) a -> Vd.1Q NOP Vd.2D -> result A32/A64 float16x8_t vreinterpretq_f16_p128(poly128_t a) a -> Vd.1Q NOP Vd.8H -> result A32/A64 -mfloat8x8_t vreinterpret_mf8_u8(uint8x8_t a) a -> Vd.8B NOP Vd.8B -> result A64 -mfloat8x16_t vreinterpretq_mf8_u8(uint8x16_t a) a -> Vd.16B NOP Vd.16B -> result A64 -uint8x8_t vreinterpret_u8_mf8(mfloat8x8_t a) a -> Vd.8B NOP Vd.8B -> result A64 -uint8x16_t vreinterpretq_u8_mf8(mfloat8x16_t a) a -> Vd.16B NOP Vd.16B -> result A64 poly128_t vldrq_p128(poly128_t const *ptr) ptr -> Xn LDR Qd,[Xn] Qd -> result A32/A64 void vstrq_p128(poly128_t *ptr, poly128_t val) val -> Qt;ptr -> Xn STR Qt,[Xn] A32/A64 From 66efbf4c68c8d1f7534c6629c2f3ec1b7b98da54 Mon Sep 17 00:00:00 2001 From: Martin Wehking Date: Mon, 20 Jul 2026 12:19:22 +0000 Subject: [PATCH 2/2] Remove extra '/' --- neon_intrinsics/advsimd.md | 2 +- tools/intrinsic_db/advsimd.csv | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/neon_intrinsics/advsimd.md b/neon_intrinsics/advsimd.md index ead91a46..76eefe0c 100644 --- a/neon_intrinsics/advsimd.md +++ b/neon_intrinsics/advsimd.md @@ -3333,7 +3333,7 @@ The intrinsics in this section are guarded by the macro ``__ARM_NEON``. | poly16x8_t vdupq_lane_p16(
     poly16x4_t vec,
     const int lane) | `vec -> Vn.4H`
`0 <= lane <= 3` | `DUP Vd.8H,Vn.H[lane]` | `Vd.8H -> result` | `v7/A32/A64` | | float64x1_t vdup_lane_f64(
     float64x1_t vec,
     const int lane) | `vec -> Vn.1D`
`0 <= lane <= 0` | `DUP Dd,Vn.D[lane]` | `Dd -> result` | `A64` | | float64x2_t vdupq_lane_f64(
     float64x1_t vec,
     const int lane) | `vec -> Vn.1D`
`0 <= lane <= 0` | `DUP Vd.2D,Vn.D[lane]` | `Vd.2D -> result` | `A64` | -| mfloat8x8_t vdup_lane_mf8(
     mfloat8x8_t vec,
     const int lane) | `vec -> Vn.8B`
`0 <= lane <= 7` | `DUP Vd.8B,Vn.B[lane]` | `Vd.8B -> result` | `/A64` | +| mfloat8x8_t vdup_lane_mf8(
     mfloat8x8_t vec,
     const int lane) | `vec -> Vn.8B`
`0 <= lane <= 7` | `DUP Vd.8B,Vn.B[lane]` | `Vd.8B -> result` | `A64` | | mfloat8x16_t vdupq_lane_mf8(
     mfloat8x8_t vec,
     const int lane) | `vec -> Vn.8B`
`0 <= lane <= 7` | `DUP Vd.16B,Vn.B[lane]` | `Vd.16B -> result` | `A64` | | int8x8_t vdup_laneq_s8(
     int8x16_t vec,
     const int lane) | `vec -> Vn.16B`
`0 <= lane <= 15` | `DUP Vd.8B,Vn.B[lane]` | `Vd.8B -> result` | `A64` | | int8x16_t vdupq_laneq_s8(
     int8x16_t vec,
     const int lane) | `vec -> Vn.16B`
`0 <= lane <= 15` | `DUP Vd.16B,Vn.B[lane]` | `Vd.16B -> result` | `A64` | diff --git a/tools/intrinsic_db/advsimd.csv b/tools/intrinsic_db/advsimd.csv index 0f490039..88a8b043 100644 --- a/tools/intrinsic_db/advsimd.csv +++ b/tools/intrinsic_db/advsimd.csv @@ -2001,7 +2001,7 @@ poly16x4_t vdup_lane_p16(poly16x4_t vec, __builtin_constant_p(lane)) vec -> Vn.4 poly16x8_t vdupq_lane_p16(poly16x4_t vec, __builtin_constant_p(lane)) vec -> Vn.4H;0 <= lane <= 3 DUP Vd.8H,Vn.H[lane] Vd.8H -> result v7/A32/A64 float64x1_t vdup_lane_f64(float64x1_t vec, __builtin_constant_p(lane)) vec -> Vn.1D;0 <= lane <= 0 DUP Dd,Vn.D[lane] Dd -> result A64 float64x2_t vdupq_lane_f64(float64x1_t vec, __builtin_constant_p(lane)) vec -> Vn.1D;0 <= lane <= 0 DUP Vd.2D,Vn.D[lane] Vd.2D -> result A64 -mfloat8x8_t vdup_lane_mf8(mfloat8x8_t vec, __builtin_constant_p(lane)) vec -> Vn.8B;0 <= lane <= 7 DUP Vd.8B,Vn.B[lane] Vd.8B -> result /A64 +mfloat8x8_t vdup_lane_mf8(mfloat8x8_t vec, __builtin_constant_p(lane)) vec -> Vn.8B;0 <= lane <= 7 DUP Vd.8B,Vn.B[lane] Vd.8B -> result A64 mfloat8x16_t vdupq_lane_mf8(mfloat8x8_t vec, __builtin_constant_p(lane)) vec -> Vn.8B;0 <= lane <= 7 DUP Vd.16B,Vn.B[lane] Vd.16B -> result A64 int8x8_t vdup_laneq_s8(int8x16_t vec, __builtin_constant_p(lane)) vec -> Vn.16B;0 <= lane <= 15 DUP Vd.8B,Vn.B[lane] Vd.8B -> result A64 int8x16_t vdupq_laneq_s8(int8x16_t vec, __builtin_constant_p(lane)) vec -> Vn.16B;0 <= lane <= 15 DUP Vd.16B,Vn.B[lane] Vd.16B -> result A64