From 3e5b5c8d3e4f36f7b9afab6f546b624e363f1206 Mon Sep 17 00:00:00 2001 From: 94xhn <87560781+94xhn@users.noreply.github.com> Date: Sat, 11 Jul 2026 22:10:54 +0800 Subject: [PATCH] fix(linker): correct cross-toolchain memory map inconsistencies in STM32N6 GCC linker scripts Cross-checked the GCC (STM32CubeIDE .ld), IAR (EWARM .icf) and Keil (MDK-ARM .sct, the real scatter file referenced by in .uvprojx, not the stale OCR_RVCT placeholders) linker descriptions of the same physical memory for every Projects/* example and found four GCC-only drifts, all confirmed by both other toolchains agreeing with each other and disagreeing with GCC: 1. PWR_STANDBY / PWR_STANDBY_RTC (STM32N6570-DK, Appli role): the GCC RAM region started at 0x34020000 while ROM (511K @ 0x34000400) ends at 0x3407FFFF, so RAM overlapped the last 384 KB of ROM. IAR and Keil both start RAM at 0x34080000 (immediately after ROM). Moved the GCC RAM origin to 0x34080000 to remove the overlap. 2. CORTEX_InterruptSwitch_TrustZone (NUCLEO-N657X0-Q, AppliNonSecure role): GCC declared only 256 KB of non-secure RAM (0x241A0000- 0x241DFFFF) while IAR (ROM_region + RAM_region) and Keil (ROM_SIZE + RAM_SIZE) both cover the full 384 KB non-secure window up to 0x241FFFFF, which is also the well-established top of that AXISRAM2 bank used consistently across the rest of the repository (secure alias 0x341FFFFF). Widened GCC's RAM LENGTH from 256K to 384K to match. 3. VENC_RTSP_Server / VENC_SDCard / VENC_SDCard_ThreadX / VENC_USB (STM32N6570-DK, FSBL role): GCC declared the FSBL RAM region as 255K instead of 256K (looks like the adjacent ROM line's 255K was copy-pasted into the RAM line). Both IAR (__ICFEDIT_region_RAM_end__ = 0x341FFFFF) and Keil (__RAM_SIZE = 0x00040000) agree the region is the full 256K. Fixed GCC RAM LENGTH from 255K to 256K in all four FSBL linker scripts. 4. VENC_SDCard (STM32N6570-DK, Appli role): the same project's ROM region was declared as a round 256K, one KB larger than IAR (__ICFEDIT_region_ROM_end__ = 0x3403FFFF -> 255K) and Keil (__ROM_SIZE = 0x0003FC00 -> 255K), inconsistent with the repo-wide convention that a ROM window starting at a +0x400 header offset is sized (bank - 1K). Fixed GCC ROM LENGTH from 256K to 255K. No local ARM toolchain available; verified purely via address arithmetic (region overlap / boundary matching) cross-referenced against the independently-authored IAR and Keil files for the same example. Several other automated mismatches were investigated and excluded as false positives, e.g. GCC merging ROM+RAM into a single named region where IAR/Keil split them (same total physical span, just a different MEMORY block style), and NetXDuo examples where GCC uses an absolute- address sub-section for the packet pool while IAR carves out a separate named region at the same address (same physical layout, different linker-script idiom). Signed-off-by: 94xhn <87560781+94xhn@users.noreply.github.com> --- .../STM32CubeIDE/AppliNonSecure/STM32N657X0HXQ_FLASH.ld | 2 +- .../STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld | 2 +- .../VENC/VENC_SDCard/STM32CubeIDE/Appli/STM32N657XX_LRUN.ld | 2 +- .../VENC_SDCard/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld | 2 +- .../STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld | 2 +- .../VENC_USB/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld | 2 +- .../PWR/PWR_STANDBY/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld | 2 +- .../PWR_STANDBY_RTC/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/Projects/NUCLEO-N657X0-Q/Examples/CORTEX/CORTEX_InterruptSwitch_TrustZone/STM32CubeIDE/AppliNonSecure/STM32N657X0HXQ_FLASH.ld b/Projects/NUCLEO-N657X0-Q/Examples/CORTEX/CORTEX_InterruptSwitch_TrustZone/STM32CubeIDE/AppliNonSecure/STM32N657X0HXQ_FLASH.ld index 2c12dfef2..a56fdbf1a 100644 --- a/Projects/NUCLEO-N657X0-Q/Examples/CORTEX/CORTEX_InterruptSwitch_TrustZone/STM32CubeIDE/AppliNonSecure/STM32N657X0HXQ_FLASH.ld +++ b/Projects/NUCLEO-N657X0-Q/Examples/CORTEX/CORTEX_InterruptSwitch_TrustZone/STM32CubeIDE/AppliNonSecure/STM32N657X0HXQ_FLASH.ld @@ -44,7 +44,7 @@ _Min_Stack_Size = 0x1000; /* required amount of stack */ /* Memories definition */ MEMORY { - RAM (xrw) : ORIGIN = 0x241a0000, LENGTH = 256K + RAM (xrw) : ORIGIN = 0x241a0000, LENGTH = 384K } /* Sections */ diff --git a/Projects/STM32N6570-DK/Applications/VENC/VENC_RTSP_Server/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld b/Projects/STM32N6570-DK/Applications/VENC/VENC_RTSP_Server/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld index f4228b7ca..b0dec2980 100644 --- a/Projects/STM32N6570-DK/Applications/VENC/VENC_RTSP_Server/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld +++ b/Projects/STM32N6570-DK/Applications/VENC/VENC_RTSP_Server/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld @@ -49,7 +49,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */ MEMORY { ROM (xr) : ORIGIN = 0x34180400, LENGTH = 255K - RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 255K + RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 256K DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K } diff --git a/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/Appli/STM32N657XX_LRUN.ld b/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/Appli/STM32N657XX_LRUN.ld index 176f09020..ffe5a6ae1 100644 --- a/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/Appli/STM32N657XX_LRUN.ld +++ b/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/Appli/STM32N657XX_LRUN.ld @@ -48,7 +48,7 @@ _eDTCM = ORIGIN(DTCM) + LENGTH(DTCM); /* Memories definition */ MEMORY { - ROM (xr) : ORIGIN = 0x34000400, LENGTH = 256K + ROM (xr) : ORIGIN = 0x34000400, LENGTH = 255K RAM (rw) : ORIGIN = 0x341B7000, LENGTH = 2340K DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K } diff --git a/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld b/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld index f4228b7ca..b0dec2980 100644 --- a/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld +++ b/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld @@ -49,7 +49,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */ MEMORY { ROM (xr) : ORIGIN = 0x34180400, LENGTH = 255K - RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 255K + RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 256K DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K } diff --git a/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard_ThreadX/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld b/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard_ThreadX/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld index f4228b7ca..b0dec2980 100644 --- a/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard_ThreadX/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld +++ b/Projects/STM32N6570-DK/Applications/VENC/VENC_SDCard_ThreadX/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld @@ -49,7 +49,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */ MEMORY { ROM (xr) : ORIGIN = 0x34180400, LENGTH = 255K - RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 255K + RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 256K DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K } diff --git a/Projects/STM32N6570-DK/Applications/VENC/VENC_USB/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld b/Projects/STM32N6570-DK/Applications/VENC/VENC_USB/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld index f4228b7ca..b0dec2980 100644 --- a/Projects/STM32N6570-DK/Applications/VENC/VENC_USB/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld +++ b/Projects/STM32N6570-DK/Applications/VENC/VENC_USB/STM32CubeIDE/FSBL/STM32N657XX_AXISRAM2_fsbl.ld @@ -49,7 +49,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */ MEMORY { ROM (xr) : ORIGIN = 0x34180400, LENGTH = 255K - RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 255K + RAM (rw) : ORIGIN = 0x341C0000, LENGTH = 256K DTCM (rw) : ORIGIN = 0x30000000, LENGTH = 128K } diff --git a/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld b/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld index 0c2627512..c16b4c84e 100644 --- a/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld +++ b/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld @@ -45,7 +45,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */ MEMORY { ROM (xrw) : ORIGIN = 0x34000400, LENGTH = 511K - RAM (xrw) : ORIGIN = 0x34020000, LENGTH = 1536K + RAM (xrw) : ORIGIN = 0x34080000, LENGTH = 1536K } /* Sections */ diff --git a/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld b/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld index 0c2627512..c16b4c84e 100644 --- a/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld +++ b/Projects/STM32N6570-DK/Examples/PWR/PWR_STANDBY_RTC/STM32CubeIDE/Appli/STM32N657X0HXQ_LRUN.ld @@ -45,7 +45,7 @@ _Min_Stack_Size = 0x800; /* required amount of stack */ MEMORY { ROM (xrw) : ORIGIN = 0x34000400, LENGTH = 511K - RAM (xrw) : ORIGIN = 0x34020000, LENGTH = 1536K + RAM (xrw) : ORIGIN = 0x34080000, LENGTH = 1536K } /* Sections */