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2660 lines (2311 loc) · 137 KB
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// Helper script for Ghidra to find and generate patterns compatible with PatternFinder
// @author TrackAndTruckDevs
// @version 1.0.0
// @category SPF-Framework
// @keybinding ctrl alt P
// @menupath Tools.SPF Pattern Helper
import ghidra.app.script.GhidraScript;
import ghidra.app.services.CodeViewerService;
import ghidra.program.model.address.Address;
import ghidra.program.model.address.AddressRange;
import ghidra.program.model.address.AddressSet;
import ghidra.program.model.listing.Function;
import ghidra.program.model.listing.Instruction;
import ghidra.program.model.listing.Listing;
import ghidra.program.model.mem.Memory;
import ghidra.program.model.mem.MemoryBlock;
import ghidra.program.util.ProgramSelection;
import javax.swing.*;
import java.awt.*;
import java.util.*;
import java.util.regex.Matcher;
import java.util.regex.Pattern;
import javax.swing.event.HyperlinkListener;
public class GhidraPatternHelper extends GhidraScript {
private static final Map<String, String> TEMPLATES = new LinkedHashMap<>();
static {
// =========================================================================
// === MOV INSTRUCTIONS ===
// =========================================================================
//
// ModRM byte (Mod /Reg /R/M) — upper 2 bits = Mod addressing mode:
// Mod=00 [00-3f] — [r64] (no displacement)
// Mod=01 [40-7f] — [r64+disp8] (8-bit displacement)
// Mod=10 [80-bf] — [r64+disp32] (32-bit displacement)
// Mod=11 [c0-ff] — register-register
// R/M=100 (0x4) — SIB byte follows (index*scale + base)
// R/M=101 (0x5) — RIP-relative (Mod=00) or disp32/64 (Mod=00)
//
// SIB byte (Scale:Index:Base):
// Scale — [7:6] = 00(x1) 01(x2) 10(x4) 11(x8)
// Index — [5:3] = register or 100=RSP (no index)
// Base — [2:0] = register or 101=RBP (no base, disp follows)
//
// REX prefix: byte 0x40-0x4F, bit W (bit 3) = 1 → 64-bit operand
// --- MOV: Register ← Immediate ---
TEMPLATES.put("[MOV r8, imm8]", "[b0-b7] ?");
TEMPLATES.put("[MOV r32, imm32]", "4[0-f]? [b8-bf] ? ? ? ?");
TEMPLATES.put("[MOV r64, imm64]", "4[8-f] [b8-bf] ? ? ? ? ? ? ? ?");
TEMPLATES.put("[MOV r64, imm32]", "4[8-f] c7 [c0-ff] ? ? ? ?");
// --- MOV: Register ← Register ---
TEMPLATES.put("[MOV r32, r32]", "8b [c0-ff]");
TEMPLATES.put("[MOV r64, r64]", "4[8-f] 8[b|9] [c0-ff]");
// --- MOV: Register ← Memory (RIP-Relative) ---
TEMPLATES.put("[MOV r8, [rip+off32]]", "8a 05 ? ? ? ?");
TEMPLATES.put("[MOV r32, [rip+off32]]", "8b [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOV r64, [rip+off32]]", "4[8-f] 8b [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
// --- MOV: Register ← Memory (r64 base + disp32) ---
TEMPLATES.put("[MOV r8, [r64+off32]]", "8a [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOV r32, [r64+off32]]", "8b [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOV r64, [r64+off32]]", "4[8-f] 8b [80-bf] [SIB?] ? ? ? ?");
// --- MOV: Register ← Memory (r64 base + disp8) ---
TEMPLATES.put("[MOV r8, [r64+off8]]", "8a [40-7f] [SIB?] ?");
TEMPLATES.put("[MOV r32, [r64+off8]]", "8b [40-7f] [SIB?] ?");
TEMPLATES.put("[MOV r64, [r64+off8]]", "4[8-f] 8b [40-7f] [SIB?] ?");
// --- MOV: Register ← Memory (r64 base, no displacement) ---
TEMPLATES.put("[MOV r8, [r64]]", "8a [00-3f] [SIB?]");
TEMPLATES.put("[MOV r32, [r64]]", "8b [00-3f] [SIB?]");
TEMPLATES.put("[MOV r64, [r64]]", "4[8-f] 8b [00-3f] [SIB?]");
// --- MOV: Memory (RIP-Relative) ← Register ---
TEMPLATES.put("[MOV [rip+off32], r8]", "88 05 ? ? ? ?");
TEMPLATES.put("[MOV [rip+off32], r32]", "4[0-f]? 89 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOV [rip+off32], r64]", "4[8-f] 89 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
// --- MOV: Memory (RIP-Relative) ← Immediate ---
TEMPLATES.put("[MOV byte ptr [rip+off32], imm8]", "c6 05 ? ? ? ? ?");
TEMPLATES.put("[MOV dword ptr [rip+off32], imm32]", "c7 05 ? ? ? ? ? ? ? ?");
// --- MOV: Memory (r64 base + disp32) ← Register ---
TEMPLATES.put("[MOV [r64+off32], r8]", "88 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOV [r64+off32], r32]", "89 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOV [r64+off32], r64]", "4[8-f] 89 [80-bf] [SIB?] ? ? ? ?");
// --- MOV: Memory (r64 base + disp8) ← Register ---
TEMPLATES.put("[MOV [r64+off8], r8]", "88 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOV [r64+off8], r32]", "89 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOV [r64+off8], r64]", "4[8-f] 89 [40-7f] [SIB?] ?");
// --- MOV: Memory (r64 base, no displacement) ← Register ---
TEMPLATES.put("[MOV [r64], r8]", "88 [00-3f] [SIB?]");
TEMPLATES.put("[MOV [r64], r32]", "89 [00-3f] [SIB?]");
TEMPLATES.put("[MOV [r64], r64]", "4[8-f] 89 [00-3f] [SIB?]");
// --- MOV: Memory (r64 base + disp32) ← Immediate ---
TEMPLATES.put("[MOV byte ptr [r64+off32], imm8]", "c6 [80-bf] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[MOV dword ptr [r64+off32], imm32]", "c7 [80-bf] [SIB?] ? ? ? ? ? ? ? ?");
TEMPLATES.put("[MOV qword ptr [r64+off32], imm64_32]", "4[8-f] c7 [80-bf] [SIB?] ? ? ? ? ? ? ? ?");
// --- MOV: Memory (r64 base + disp8) ← Immediate ---
TEMPLATES.put("[MOV byte ptr [r64+off8], imm8]", "c6 [40-7f] [SIB?] ? ?");
TEMPLATES.put("[MOV dword ptr [r64+off8], imm32]", "c7 [40-7f] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[MOV qword ptr [r64+off8], imm64_32]", "4[8-f] c7 [40-7f] [SIB?] ? ? ? ? ?");
// --- MOV: SIB-specific Load (ModRM R/M=100, register ← memory) ---
TEMPLATES.put("[MOV r8, [r64+sib+off32]]", "8a [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOV r8, [r64+sib+off8]]", "8a [44-7c] ? ? ?");
TEMPLATES.put("[MOV r8, [r64+sib]]", "8a [04-3c] ?");
TEMPLATES.put("[MOV r32, [r64+sib+off32]]", "8b [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOV r32, [r64+sib+off8]]", "8b [44-7c] ? ? ?");
TEMPLATES.put("[MOV r32, [r64+sib]]", "8b [04-3c] ?");
TEMPLATES.put("[MOV r64, [r64+sib+off32]]", "4[8-f] 8b [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOV r64, [r64+sib+off8]]", "4[8-f] 8b [44-7c] ? ? ?");
TEMPLATES.put("[MOV r64, [r64+sib]]", "4[8-f] 8b [04-3c] ?");
// --- MOV: SIB-specific Store (ModRM R/M=100, memory ← register) ---
TEMPLATES.put("[MOV [r64+sib+off32], r8]", "88 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOV [r64+sib+off8], r8]", "88 [44-7c] ? ? ?");
TEMPLATES.put("[MOV [r64+sib], r8]", "88 [04-3c] ?");
TEMPLATES.put("[MOV [r64+sib+off32], r32]", "89 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOV [r64+sib+off8], r32]", "89 [44-7c] ? ? ?");
TEMPLATES.put("[MOV [r64+sib], r32]", "89 [04-3c] ?");
TEMPLATES.put("[MOV [r64+sib+off32], r64]", "4[8-f] 89 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOV [r64+sib+off8], r64]", "4[8-f] 89 [44-7c] ? ? ?");
TEMPLATES.put("[MOV [r64+sib], r64]", "4[8-f] 89 [04-3c] ?");
// --- MOV: Zero Extend (MOVZX) ---
TEMPLATES.put("[MOVZX r32, [r64]]", "0f b6 [00-3f] [SIB?]");
TEMPLATES.put("[MOVZX r32, [r64+off8]]", "0f b6 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVZX r32, [r64+off32]]", "0f b6 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVZX r64, [r64+off8]]", "4[8-f] 0f b6 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVZX r64, [r64+off32]]", "4[8-f] 0f b6 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVZX r32, w[r64]]", "0f b7 [00-3f] [SIB?]");
TEMPLATES.put("[MOVZX r32, w[r64+off8]]", "0f b7 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVZX r32, w[r64+off32]]", "0f b7 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVZX r32, r8]", "0f b6 [c0-ff]");
TEMPLATES.put("[MOVZX r64, r8]", "4[8-f] 0f b6 [c0-ff]");
// --- MOV: Sign Extend (MOVSXD) ---
TEMPLATES.put("[MOVSXD r64, r32]", "4[8-f] 63 [c0-ff]");
TEMPLATES.put("[MOVSXD r64, [r64+off8]]", "4[8-f] 63 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSXD r64, [r64+off32]]", "4[8-f] 63 [80-bf] [SIB?] ? ? ? ?");
// --- MOVSX: Sign Extend (Byte/Word to Dword/Qword) ---
TEMPLATES.put("[MOVSX r32, [r64]]", "0f be [00-3f] [SIB?]");
TEMPLATES.put("[MOVSX r32, [r64+off8]]", "0f be [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSX r32, [r64+off32]]", "0f be [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVSX r64, [r64+off8]]", "4[8-f] 0f be [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSX r64, [r64+off32]]", "4[8-f] 0f be [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVSX r32, w[r64]]", "0f bf [00-3f] [SIB?]");
TEMPLATES.put("[MOVSX r32, w[r64+off8]]", "0f bf [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSX r32, w[r64+off32]]", "0f bf [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVSX r64, w[r64+off8]]", "4[8-f] 0f bf [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSX r64, w[r64+off32]]", "4[8-f] 0f bf [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVSX r32, r8]", "0f be [c0-ff]");
TEMPLATES.put("[MOVSX r64, r8]", "4[8-f] 0f be [c0-ff]");
TEMPLATES.put("[MOVSX r32, r16]", "0f bf [c0-ff]");
TEMPLATES.put("[MOVSX r64, r16]", "4[8-f] 0f bf [c0-ff]");
// =========================================================================
// === LEA (LOAD EFFECTIVE ADDRESS) ===
// =========================================================================
// --- LEA: Register ← Address (64-bit operand) ---
TEMPLATES.put("[LEA r64, [rip+off32]]", "4[8-f] 8d [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[LEA r64, [r64+off32]]", "4[8-f] 8d [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[LEA r64, [r64+off8]]", "4[8-f] 8d [40-7f] [SIB?] ?");
TEMPLATES.put("[LEA r64, [r64]]", "4[8-f] 8d [00-3f] [SIB?]");
// --- LEA: Register ← Address (32-bit operand) ---
TEMPLATES.put("[LEA r32, [rip+off32]]", "8d [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[LEA r32, [r64+off32]]", "8d [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[LEA r32, [r64+off8]]", "8d [40-7f] [SIB?] ?");
TEMPLATES.put("[LEA r32, [r64]]", "8d [00-3f] [SIB?]");
// --- LEA: Register ← Address (16-bit operand) ---
TEMPLATES.put("[LEA r16, [rip+off32]]", "66 8d [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[LEA r16, [r64+off8]]", "66 8d [40-7f] [SIB?] ?");
TEMPLATES.put("[LEA r16, [r64]]", "66 8d [00-3f] [SIB?]");
// --- LEA: SIB-specific (ModRM R/M=100) ---
TEMPLATES.put("[LEA r64, [r64+sib+off32]]", "4[8-f] 8d [84-bc] ? ? ? ? ?");
TEMPLATES.put("[LEA r64, [r64+sib+off8]]", "4[8-f] 8d [44-7c] ? ? ?");
TEMPLATES.put("[LEA r64, [r64+sib]]", "4[8-f] 8d [04-3c] ?");
TEMPLATES.put("[LEA r32, [r64+sib+off32]]", "8d [84-bc] ? ? ? ? ?");
TEMPLATES.put("[LEA r32, [r64+sib+off8]]", "8d [44-7c] ? ? ?");
TEMPLATES.put("[LEA r32, [r64+sib]]", "8d [04-3c] ?");
// =========================================================================
// === ARITHMETIC & LOGIC ===
// =========================================================================
// --- ADD: Register ← Register ---
TEMPLATES.put("[ADD r64, r64]", "4[8-f] [01|03] [c0-ff]");
TEMPLATES.put("[ADD r32, r32]", "[01|03] [c0-ff]");
TEMPLATES.put("[ADD r8, r8]", "[00|02] [c0-ff]");
// --- ADD: Register ← Immediate ---
TEMPLATES.put("[ADD r64, imm32]", "4[8-f] 81 [c0-c7] ? ? ? ?");
TEMPLATES.put("[ADD r32, imm32]", "81 [c0-c7] ? ? ? ?");
TEMPLATES.put("[ADD r8, imm8]", "80 [c0-c7] ?");
TEMPLATES.put("[ADD r64, imm8]", "4[8-f] 83 [c0-c7] ?");
TEMPLATES.put("[ADD r32, imm8]", "83 [c0-c7] ?");
// --- ADD: Register ← Memory (RIP-Relative) ---
TEMPLATES.put("[ADD r8, [rip+off32]]", "02 05 ? ? ? ?");
TEMPLATES.put("[ADD r32, [rip+off32]]", "03 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[ADD r64, [rip+off32]]", "4[8-f] 03 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
// --- ADD: Register ← Memory (r64 base + disp32) ---
TEMPLATES.put("[ADD r8, [r64+off32]]", "02 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[ADD r32, [r64+off32]]", "03 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[ADD r64, [r64+off32]]", "4[8-f] 03 [80-bf] [SIB?] ? ? ? ?");
// --- ADD: Register ← Memory (r64 base + disp8) ---
TEMPLATES.put("[ADD r8, [r64+off8]]", "02 [40-7f] [SIB?] ?");
TEMPLATES.put("[ADD r32, [r64+off8]]", "03 [40-7f] [SIB?] ?");
TEMPLATES.put("[ADD r64, [r64+off8]]", "4[8-f] 03 [40-7f] [SIB?] ?");
// --- ADD: Register ← Memory (r64 base, no displacement) ---
TEMPLATES.put("[ADD r8, [r64]]", "02 [00-3f] [SIB?]");
TEMPLATES.put("[ADD r32, [r64]]", "03 [00-3f] [SIB?]");
TEMPLATES.put("[ADD r64, [r64]]", "4[8-f] 03 [00-3f] [SIB?]");
// --- ADD: Memory (RIP-Relative) ← Register ---
TEMPLATES.put("[ADD [rip+off32], r8]", "00 05 ? ? ? ?");
TEMPLATES.put("[ADD [rip+off32], r32]", "01 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[ADD [rip+off32], r64]", "4[8-f] 01 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
// --- ADD: Memory (r64 base + disp32) ← Register ---
TEMPLATES.put("[ADD [r64+off32], r8]", "00 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[ADD [r64+off32], r32]", "01 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[ADD [r64+off32], r64]", "4[8-f] 01 [80-bf] [SIB?] ? ? ? ?");
// --- ADD: Memory (r64 base + disp8) ← Register ---
TEMPLATES.put("[ADD [r64+off8], r8]", "00 [40-7f] [SIB?] ?");
TEMPLATES.put("[ADD [r64+off8], r32]", "01 [40-7f] [SIB?] ?");
TEMPLATES.put("[ADD [r64+off8], r64]", "4[8-f] 01 [40-7f] [SIB?] ?");
// --- ADD: Memory (r64 base, no displacement) ← Register ---
TEMPLATES.put("[ADD [r64], r8]", "00 [00-3f] [SIB?]");
TEMPLATES.put("[ADD [r64], r32]", "01 [00-3f] [SIB?]");
TEMPLATES.put("[ADD [r64], r64]", "4[8-f] 01 [00-3f] [SIB?]");
// --- ADD: Memory (r64 base + disp32) ← Immediate ---
TEMPLATES.put("[ADD byte ptr [r64+off32], imm8]", "80 [80-87] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[ADD dword ptr [r64+off32], imm32]", "81 [80-87] [SIB?] ? ? ? ? ? ? ? ?");
TEMPLATES.put("[ADD qword ptr [r64+off32], imm64_32]", "4[8-f] 81 [80-87] [SIB?] ? ? ? ? ? ? ? ?");
// --- ADD: Memory (r64 base + disp8) ← Immediate ---
TEMPLATES.put("[ADD byte ptr [r64+off8], imm8]", "80 [40-47] [SIB?] ? ?");
TEMPLATES.put("[ADD dword ptr [r64+off8], imm32]", "81 [40-47] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[ADD qword ptr [r64+off8], imm64_32]", "4[8-f] 81 [40-47] [SIB?] ? ? ? ? ?");
// --- ADD: Memory (RIP-Relative) ← Immediate ---
TEMPLATES.put("[ADD byte ptr [rip+off32], imm8]", "80 05 ? ? ? ? ?");
TEMPLATES.put("[ADD dword ptr [rip+off32], imm32]", "81 05 ? ? ? ? ? ? ? ?");
TEMPLATES.put("[ADD qword ptr [rip+off32], imm64_32]", "4[8-f] 81 05 ? ? ? ? ? ? ? ?");
// --- ADD: SIB-specific Load (ModRM R/M=100, register ← memory) ---
TEMPLATES.put("[ADD r8, [r64+sib+off32]]", "02 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[ADD r8, [r64+sib+off8]]", "02 [44-7c] ? ? ?");
TEMPLATES.put("[ADD r8, [r64+sib]]", "02 [04-3c] ?");
TEMPLATES.put("[ADD r32, [r64+sib+off32]]", "03 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[ADD r32, [r64+sib+off8]]", "03 [44-7c] ? ? ?");
TEMPLATES.put("[ADD r32, [r64+sib]]", "03 [04-3c] ?");
TEMPLATES.put("[ADD r64, [r64+sib+off32]]", "4[8-f] 03 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[ADD r64, [r64+sib+off8]]", "4[8-f] 03 [44-7c] ? ? ?");
TEMPLATES.put("[ADD r64, [r64+sib]]", "4[8-f] 03 [04-3c] ?");
// --- ADD: SIB-specific Store (ModRM R/M=100, memory ← register) ---
TEMPLATES.put("[ADD [r64+sib+off32], r8]", "00 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[ADD [r64+sib+off8], r8]", "00 [44-7c] ? ? ?");
TEMPLATES.put("[ADD [r64+sib], r8]", "00 [04-3c] ?");
TEMPLATES.put("[ADD [r64+sib+off32], r32]", "01 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[ADD [r64+sib+off8], r32]", "01 [44-7c] ? ? ?");
TEMPLATES.put("[ADD [r64+sib], r32]", "01 [04-3c] ?");
TEMPLATES.put("[ADD [r64+sib+off32], r64]", "4[8-f] 01 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[ADD [r64+sib+off8], r64]", "4[8-f] 01 [44-7c] ? ? ?");
TEMPLATES.put("[ADD [r64+sib], r64]", "4[8-f] 01 [04-3c] ?");
// --- SUB: Register ← Register ---
TEMPLATES.put("[SUB r64, r64]", "4[8-f] [29|2b] [c0-ff]");
TEMPLATES.put("[SUB r32, r32]", "[29|2b] [c0-ff]");
TEMPLATES.put("[SUB r8, r8]", "[28|2a] [c0-ff]");
// --- SUB: Register ← Immediate ---
TEMPLATES.put("[SUB r64, imm32]", "4[8-f] 81 [e8-ef] ? ? ? ?");
TEMPLATES.put("[SUB r32, imm32]", "81 [e8-ef] ? ? ? ?");
TEMPLATES.put("[SUB r8, imm8]", "80 [e8-ef] ?");
TEMPLATES.put("[SUB r64, imm8]", "4[8-f] 83 [e8-ef] ?");
TEMPLATES.put("[SUB r32, imm8]", "83 [e8-ef] ?");
// --- SUB: Register ← Memory (RIP-Relative) ---
TEMPLATES.put("[SUB r8, [rip+off32]]", "2a 05 ? ? ? ?");
TEMPLATES.put("[SUB r32, [rip+off32]]", "2b [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[SUB r64, [rip+off32]]", "4[8-f] 2b [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
// --- SUB: Register ← Memory (r64 base + disp32) ---
TEMPLATES.put("[SUB r8, [r64+off32]]", "2a [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[SUB r32, [r64+off32]]", "2b [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[SUB r64, [r64+off32]]", "4[8-f] 2b [80-bf] [SIB?] ? ? ? ?");
// --- SUB: Register ← Memory (r64 base + disp8) ---
TEMPLATES.put("[SUB r8, [r64+off8]]", "2a [40-7f] [SIB?] ?");
TEMPLATES.put("[SUB r32, [r64+off8]]", "2b [40-7f] [SIB?] ?");
TEMPLATES.put("[SUB r64, [r64+off8]]", "4[8-f] 2b [40-7f] [SIB?] ?");
// --- SUB: Register ← Memory (r64 base, no displacement) ---
TEMPLATES.put("[SUB r8, [r64]]", "2a [00-3f] [SIB?]");
TEMPLATES.put("[SUB r32, [r64]]", "2b [00-3f] [SIB?]");
TEMPLATES.put("[SUB r64, [r64]]", "4[8-f] 2b [00-3f] [SIB?]");
// --- SUB: Memory (RIP-Relative) ← Register ---
TEMPLATES.put("[SUB [rip+off32], r8]", "28 2d ? ? ? ?");
TEMPLATES.put("[SUB [rip+off32], r32]", "29 2d ? ? ? ?");
TEMPLATES.put("[SUB [rip+off32], r64]", "4[8-f] 29 2d ? ? ? ?");
// --- SUB: Memory (r64 base + disp32) ← Register ---
TEMPLATES.put("[SUB [r64+off32], r8]", "28 [a8-af] [SIB?] ? ? ? ?");
TEMPLATES.put("[SUB [r64+off32], r32]", "29 [a8-af] [SIB?] ? ? ? ?");
TEMPLATES.put("[SUB [r64+off32], r64]", "4[8-f] 29 [a8-af] [SIB?] ? ? ? ?");
// --- SUB: Memory (r64 base + disp8) ← Register ---
TEMPLATES.put("[SUB [r64+off8], r8]", "28 [68-6f] [SIB?] ?");
TEMPLATES.put("[SUB [r64+off8], r32]", "29 [68-6f] [SIB?] ?");
TEMPLATES.put("[SUB [r64+off8], r64]", "4[8-f] 29 [68-6f] [SIB?] ?");
// --- SUB: Memory (r64 base, no displacement) ← Register ---
TEMPLATES.put("[SUB [r64], r8]", "28 [28-2f] [SIB?]");
TEMPLATES.put("[SUB [r64], r32]", "29 [28-2f] [SIB?]");
TEMPLATES.put("[SUB [r64], r64]", "4[8-f] 29 [28-2f] [SIB?]");
// --- SUB: Memory (r64 base + disp32) ← Immediate ---
TEMPLATES.put("[SUB byte ptr [r64+off32], imm8]", "80 [a8-af] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[SUB dword ptr [r64+off32], imm32]", "81 [a8-af] [SIB?] ? ? ? ? ? ? ? ?");
TEMPLATES.put("[SUB qword ptr [r64+off32], imm64_32]", "4[8-f] 81 [a8-af] [SIB?] ? ? ? ? ? ? ? ?");
// --- SUB: Memory (r64 base + disp8) ← Immediate ---
TEMPLATES.put("[SUB byte ptr [r64+off8], imm8]", "80 [68-6f] [SIB?] ? ?");
TEMPLATES.put("[SUB dword ptr [r64+off8], imm32]", "81 [68-6f] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[SUB qword ptr [r64+off8], imm64_32]", "4[8-f] 81 [68-6f] [SIB?] ? ? ? ? ?");
// --- SUB: Memory (RIP-Relative) ← Immediate ---
TEMPLATES.put("[SUB byte ptr [rip+off32], imm8]", "80 2d ? ? ? ? ?");
TEMPLATES.put("[SUB dword ptr [rip+off32], imm32]", "81 2d ? ? ? ? ? ? ? ?");
TEMPLATES.put("[SUB qword ptr [rip+off32], imm64_32]", "4[8-f] 81 2d ? ? ? ? ? ? ? ?");
// --- SUB: SIB-specific Load (ModRM R/M=100, register ← memory) ---
TEMPLATES.put("[SUB r8, [r64+sib+off32]]", "2a [84-bc] ? ? ? ? ?");
TEMPLATES.put("[SUB r8, [r64+sib+off8]]", "2a [44-7c] ? ? ?");
TEMPLATES.put("[SUB r8, [r64+sib]]", "2a [04-3c] ?");
TEMPLATES.put("[SUB r32, [r64+sib+off32]]", "2b [84-bc] ? ? ? ? ?");
TEMPLATES.put("[SUB r32, [r64+sib+off8]]", "2b [44-7c] ? ? ?");
TEMPLATES.put("[SUB r32, [r64+sib]]", "2b [04-3c] ?");
TEMPLATES.put("[SUB r64, [r64+sib+off32]]", "4[8-f] 2b [84-bc] ? ? ? ? ?");
TEMPLATES.put("[SUB r64, [r64+sib+off8]]", "4[8-f] 2b [44-7c] ? ? ?");
TEMPLATES.put("[SUB r64, [r64+sib]]", "4[8-f] 2b [04-3c] ?");
// --- SUB: SIB-specific Store (ModRM R/M=100, memory ← register) ---
TEMPLATES.put("[SUB [r64+sib+off32], r8]", "28 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[SUB [r64+sib+off8], r8]", "28 [44-7c] ? ? ?");
TEMPLATES.put("[SUB [r64+sib], r8]", "28 [04-3c] ?");
TEMPLATES.put("[SUB [r64+sib+off32], r32]", "29 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[SUB [r64+sib+off8], r32]", "29 [44-7c] ? ? ?");
TEMPLATES.put("[SUB [r64+sib], r32]", "29 [04-3c] ?");
TEMPLATES.put("[SUB [r64+sib+off32], r64]", "4[8-f] 29 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[SUB [r64+sib+off8], r64]", "4[8-f] 29 [44-7c] ? ? ?");
TEMPLATES.put("[SUB [r64+sib], r64]", "4[8-f] 29 [04-3c] ?");
// --- XOR: Register ← Register ---
TEMPLATES.put("[XOR r64, r64]", "4[8-f] [31|33] [c0-ff]");
TEMPLATES.put("[XOR r32, r32]", "[31|33] [c0-ff]");
TEMPLATES.put("[XOR r16, r16]", "66 [31|33] [c0-ff]");
TEMPLATES.put("[XOR r8, r8]", "[30|32] [c0-ff]");
// --- XOR: Register ← Immediate ---
TEMPLATES.put("[XOR r64, imm32]", "4[8-f] 81 [f0-f7] ? ? ? ?");
TEMPLATES.put("[XOR r32, imm32]", "81 [f0-f7] ? ? ? ?");
TEMPLATES.put("[XOR r8, imm8]", "80 [f0-f7] ?");
TEMPLATES.put("[XOR r64, imm8]", "4[8-f] 83 [f0-f7] ?");
TEMPLATES.put("[XOR r32, imm8]", "83 [f0-f7] ?");
// --- XOR: Register ← Memory (RIP-Relative) ---
TEMPLATES.put("[XOR r8, [rip+off32]]", "32 35 ? ? ? ?");
TEMPLATES.put("[XOR r32, [rip+off32]]", "33 35 ? ? ? ?");
TEMPLATES.put("[XOR r64, [rip+off32]]", "4[8-f] 33 35 ? ? ? ?");
// --- XOR: Register ← Memory (r64 base + disp32) ---
TEMPLATES.put("[XOR r8, [r64+off32]]", "32 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[XOR r32, [r64+off32]]", "33 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[XOR r64, [r64+off32]]", "4[8-f] 33 [80-bf] [SIB?] ? ? ? ?");
// --- XOR: Register ← Memory (r64 base + disp8) ---
TEMPLATES.put("[XOR r8, [r64+off8]]", "32 [40-7f] [SIB?] ?");
TEMPLATES.put("[XOR r32, [r64+off8]]", "33 [40-7f] [SIB?] ?");
TEMPLATES.put("[XOR r64, [r64+off8]]", "4[8-f] 33 [40-7f] [SIB?] ?");
// --- XOR: Register ← Memory (r64 base, no displacement) ---
TEMPLATES.put("[XOR r8, [r64]]", "32 [00-3f] [SIB?]");
TEMPLATES.put("[XOR r32, [r64]]", "33 [00-3f] [SIB?]");
TEMPLATES.put("[XOR r64, [r64]]", "4[8-f] 33 [00-3f] [SIB?]");
// --- XOR: Memory (RIP-Relative) ← Register ---
TEMPLATES.put("[XOR [rip+off32], r8]", "30 35 ? ? ? ?");
TEMPLATES.put("[XOR [rip+off32], r32]", "31 35 ? ? ? ?");
TEMPLATES.put("[XOR [rip+off32], r64]", "4[8-f] 31 35 ? ? ? ?");
// --- XOR: Memory (r64 base + disp32) ← Register ---
TEMPLATES.put("[XOR [r64+off32], r8]", "30 [b0-b7] [SIB?] ? ? ? ?");
TEMPLATES.put("[XOR [r64+off32], r32]", "31 [b0-b7] [SIB?] ? ? ? ?");
TEMPLATES.put("[XOR [r64+off32], r64]", "4[8-f] 31 [b0-b7] [SIB?] ? ? ? ?");
// --- XOR: Memory (r64 base + disp8) ← Register ---
TEMPLATES.put("[XOR [r64+off8], r8]", "30 [70-77] [SIB?] ?");
TEMPLATES.put("[XOR [r64+off8], r32]", "31 [70-77] [SIB?] ?");
TEMPLATES.put("[XOR [r64+off8], r64]", "4[8-f] 31 [70-77] [SIB?] ?");
// --- XOR: Memory (r64 base, no displacement) ← Register ---
TEMPLATES.put("[XOR [r64], r8]", "30 [30-37] [SIB?]");
TEMPLATES.put("[XOR [r64], r32]", "31 [30-37] [SIB?]");
TEMPLATES.put("[XOR [r64], r64]", "4[8-f] 31 [30-37] [SIB?]");
// --- XOR: Memory (r64 base + disp32) ← Immediate ---
TEMPLATES.put("[XOR byte ptr [r64+off32], imm8]", "80 [b0-b7] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[XOR dword ptr [r64+off32], imm32]", "81 [b0-b7] [SIB?] ? ? ? ? ? ? ? ?");
TEMPLATES.put("[XOR qword ptr [r64+off32], imm64_32]", "4[8-f] 81 [b0-b7] [SIB?] ? ? ? ? ? ? ? ?");
// --- XOR: Memory (r64 base + disp8) ← Immediate ---
TEMPLATES.put("[XOR byte ptr [r64+off8], imm8]", "80 [70-77] [SIB?] ? ?");
TEMPLATES.put("[XOR dword ptr [r64+off8], imm32]", "81 [70-77] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[XOR qword ptr [r64+off8], imm64_32]", "4[8-f] 81 [70-77] [SIB?] ? ? ? ? ?");
// --- XOR: Memory (RIP-Relative) ← Immediate ---
TEMPLATES.put("[XOR byte ptr [rip+off32], imm8]", "80 35 ? ? ? ? ?");
TEMPLATES.put("[XOR dword ptr [rip+off32], imm32]", "81 35 ? ? ? ? ? ? ? ?");
TEMPLATES.put("[XOR qword ptr [rip+off32], imm64_32]", "4[8-f] 81 35 ? ? ? ? ? ? ? ?");
// --- XOR: SIB-specific Load (ModRM R/M=100, register ← memory) ---
TEMPLATES.put("[XOR r8, [r64+sib+off32]]", "32 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[XOR r8, [r64+sib+off8]]", "32 [44-7c] ? ? ?");
TEMPLATES.put("[XOR r8, [r64+sib]]", "32 [04-3c] ?");
TEMPLATES.put("[XOR r32, [r64+sib+off32]]", "33 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[XOR r32, [r64+sib+off8]]", "33 [44-7c] ? ? ?");
TEMPLATES.put("[XOR r32, [r64+sib]]", "33 [04-3c] ?");
TEMPLATES.put("[XOR r64, [r64+sib+off32]]", "4[8-f] 33 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[XOR r64, [r64+sib+off8]]", "4[8-f] 33 [44-7c] ? ? ?");
TEMPLATES.put("[XOR r64, [r64+sib]]", "4[8-f] 33 [04-3c] ?");
// --- XOR: SIB-specific Store (ModRM R/M=100, memory ← register) ---
TEMPLATES.put("[XOR [r64+sib+off32], r8]", "30 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[XOR [r64+sib+off8], r8]", "30 [44-7c] ? ? ?");
TEMPLATES.put("[XOR [r64+sib], r8]", "30 [04-3c] ?");
TEMPLATES.put("[XOR [r64+sib+off32], r32]", "31 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[XOR [r64+sib+off8], r32]", "31 [44-7c] ? ? ?");
TEMPLATES.put("[XOR [r64+sib], r32]", "31 [04-3c] ?");
TEMPLATES.put("[XOR [r64+sib+off32], r64]", "4[8-f] 31 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[XOR [r64+sib+off8], r64]", "4[8-f] 31 [44-7c] ? ? ?");
TEMPLATES.put("[XOR [r64+sib], r64]", "4[8-f] 31 [04-3c] ?");
// --- AND: Register ← Register ---
TEMPLATES.put("[AND r64, r64]", "4[8-f] [21|23] [c0-ff]");
TEMPLATES.put("[AND r32, r32]", "[21|23] [c0-ff]");
TEMPLATES.put("[AND r8, r8]", "[20|22] [c0-ff]");
// --- AND: Register ← Immediate ---
TEMPLATES.put("[AND r64, imm32]", "4[8-f] 81 [e0-e7] ? ? ? ?");
TEMPLATES.put("[AND r32, imm32]", "81 [e0-e7] ? ? ? ?");
TEMPLATES.put("[AND r8, imm8]", "80 [e0-e7] ?");
TEMPLATES.put("[AND r64, imm8]", "4[8-f] 83 [e0-e7] ?");
TEMPLATES.put("[AND r32, imm8]", "83 [e0-e7] ?");
TEMPLATES.put("[AND AL, imm8]", "24 ?");
TEMPLATES.put("[AND EAX, imm32]", "25 ? ? ? ?");
// --- AND: Register ← Memory (RIP-Relative) ---
TEMPLATES.put("[AND r8, [rip+off32]]", "22 25 ? ? ? ?");
TEMPLATES.put("[AND r32, [rip+off32]]", "23 25 ? ? ? ?");
TEMPLATES.put("[AND r64, [rip+off32]]", "4[8-f] 23 25 ? ? ? ?");
// --- AND: Register ← Memory (r64 base + disp32) ---
TEMPLATES.put("[AND r8, [r64+off32]]", "22 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[AND r32, [r64+off32]]", "23 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[AND r64, [r64+off32]]", "4[8-f] 23 [80-bf] [SIB?] ? ? ? ?");
// --- AND: Register ← Memory (r64 base + disp8) ---
TEMPLATES.put("[AND r8, [r64+off8]]", "22 [40-7f] [SIB?] ?");
TEMPLATES.put("[AND r32, [r64+off8]]", "23 [40-7f] [SIB?] ?");
TEMPLATES.put("[AND r64, [r64+off8]]", "4[8-f] 23 [40-7f] [SIB?] ?");
// --- AND: Register ← Memory (r64 base, no displacement) ---
TEMPLATES.put("[AND r8, [r64]]", "22 [00-3f] [SIB?]");
TEMPLATES.put("[AND r32, [r64]]", "23 [00-3f] [SIB?]");
TEMPLATES.put("[AND r64, [r64]]", "4[8-f] 23 [00-3f] [SIB?]");
// --- AND: Memory (RIP-Relative) ← Register ---
TEMPLATES.put("[AND [rip+off32], r8]", "20 25 ? ? ? ?");
TEMPLATES.put("[AND [rip+off32], r32]", "21 25 ? ? ? ?");
TEMPLATES.put("[AND [rip+off32], r64]", "4[8-f] 21 25 ? ? ? ?");
// --- AND: Memory (r64 base + disp32) ← Register ---
TEMPLATES.put("[AND [r64+off32], r8]", "20 [a0-a7] [SIB?] ? ? ? ?");
TEMPLATES.put("[AND [r64+off32], r32]", "21 [a0-a7] [SIB?] ? ? ? ?");
TEMPLATES.put("[AND [r64+off32], r64]", "4[8-f] 21 [a0-a7] [SIB?] ? ? ? ?");
// --- AND: Memory (r64 base + disp8) ← Register ---
TEMPLATES.put("[AND [r64+off8], r8]", "20 [60-67] [SIB?] ?");
TEMPLATES.put("[AND [r64+off8], r32]", "21 [60-67] [SIB?] ?");
TEMPLATES.put("[AND [r64+off8], r64]", "4[8-f] 21 [60-67] [SIB?] ?");
// --- AND: Memory (r64 base, no displacement) ← Register ---
TEMPLATES.put("[AND [r64], r8]", "20 [20-27] [SIB?]");
TEMPLATES.put("[AND [r64], r32]", "21 [20-27] [SIB?]");
TEMPLATES.put("[AND [r64], r64]", "4[8-f] 21 [20-27] [SIB?]");
// --- AND: Memory (r64 base + disp32) ← Immediate ---
TEMPLATES.put("[AND byte ptr [r64+off32], imm8]", "80 [a0-a7] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[AND dword ptr [r64+off32], imm32]", "81 [a0-a7] [SIB?] ? ? ? ? ? ? ? ?");
TEMPLATES.put("[AND qword ptr [r64+off32], imm64_32]", "4[8-f] 81 [a0-a7] [SIB?] ? ? ? ? ? ? ? ?");
// --- AND: Memory (r64 base + disp8) ← Immediate ---
TEMPLATES.put("[AND byte ptr [r64+off8], imm8]", "80 [60-67] [SIB?] ? ?");
TEMPLATES.put("[AND dword ptr [r64+off8], imm32]", "81 [60-67] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[AND qword ptr [r64+off8], imm64_32]", "4[8-f] 81 [60-67] [SIB?] ? ? ? ? ?");
// --- AND: Memory (RIP-Relative) ← Immediate ---
TEMPLATES.put("[AND byte ptr [rip+off32], imm8]", "80 25 ? ? ? ? ?");
TEMPLATES.put("[AND dword ptr [rip+off32], imm32]", "81 25 ? ? ? ? ? ? ? ?");
TEMPLATES.put("[AND qword ptr [rip+off32], imm64_32]", "4[8-f] 81 25 ? ? ? ? ? ? ? ?");
// --- AND: SIB-specific Load (ModRM R/M=100, register ← memory) ---
TEMPLATES.put("[AND r8, [r64+sib+off32]]", "22 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[AND r8, [r64+sib+off8]]", "22 [44-7c] ? ? ?");
TEMPLATES.put("[AND r8, [r64+sib]]", "22 [04-3c] ?");
TEMPLATES.put("[AND r32, [r64+sib+off32]]", "23 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[AND r32, [r64+sib+off8]]", "23 [44-7c] ? ? ?");
TEMPLATES.put("[AND r32, [r64+sib]]", "23 [04-3c] ?");
TEMPLATES.put("[AND r64, [r64+sib+off32]]", "4[8-f] 23 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[AND r64, [r64+sib+off8]]", "4[8-f] 23 [44-7c] ? ? ?");
TEMPLATES.put("[AND r64, [r64+sib]]", "4[8-f] 23 [04-3c] ?");
// --- AND: SIB-specific Store (ModRM R/M=100, memory ← register) ---
TEMPLATES.put("[AND [r64+sib+off32], r8]", "20 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[AND [r64+sib+off8], r8]", "20 [44-7c] ? ? ?");
TEMPLATES.put("[AND [r64+sib], r8]", "20 [04-3c] ?");
TEMPLATES.put("[AND [r64+sib+off32], r32]", "21 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[AND [r64+sib+off8], r32]", "21 [44-7c] ? ? ?");
TEMPLATES.put("[AND [r64+sib], r32]", "21 [04-3c] ?");
TEMPLATES.put("[AND [r64+sib+off32], r64]", "4[8-f] 21 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[AND [r64+sib+off8], r64]", "4[8-f] 21 [44-7c] ? ? ?");
TEMPLATES.put("[AND [r64+sib], r64]", "4[8-f] 21 [04-3c] ?");
// --- OR: Register ← Register ---
TEMPLATES.put("[OR r64, r64]", "4[8-f] [09|0b] [c0-ff]");
TEMPLATES.put("[OR r32, r32]", "[09|0b] [c0-ff]");
TEMPLATES.put("[OR r8, r8]", "[08|0a] [c0-ff]");
// --- OR: Register ← Immediate ---
TEMPLATES.put("[OR r64, imm32]", "4[8-f] 81 [c8-cf] ? ? ? ?");
TEMPLATES.put("[OR r32, imm32]", "81 [c8-cf] ? ? ? ?");
TEMPLATES.put("[OR r8, imm8]", "80 [c8-cf] ?");
TEMPLATES.put("[OR r64, imm8]", "4[8-f] 83 [c8-cf] ?");
TEMPLATES.put("[OR r32, imm8]", "83 [c8-cf] ?");
// --- OR: Register ← Memory (RIP-Relative) ---
TEMPLATES.put("[OR r8, [rip+off32]]", "0a 0d ? ? ? ?");
TEMPLATES.put("[OR r32, [rip+off32]]", "0b 0d ? ? ? ?");
TEMPLATES.put("[OR r64, [rip+off32]]", "4[8-f] 0b 0d ? ? ? ?");
// --- OR: Register ← Memory (r64 base + disp32) ---
TEMPLATES.put("[OR r8, [r64+off32]]", "0a [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[OR r32, [r64+off32]]", "0b [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[OR r64, [r64+off32]]", "4[8-f] 0b [80-bf] [SIB?] ? ? ? ?");
// --- OR: Register ← Memory (r64 base + disp8) ---
TEMPLATES.put("[OR r8, [r64+off8]]", "0a [40-7f] [SIB?] ?");
TEMPLATES.put("[OR r32, [r64+off8]]", "0b [40-7f] [SIB?] ?");
TEMPLATES.put("[OR r64, [r64+off8]]", "4[8-f] 0b [40-7f] [SIB?] ?");
// --- OR: Register ← Memory (r64 base, no displacement) ---
TEMPLATES.put("[OR r8, [r64]]", "0a [00-3f] [SIB?]");
TEMPLATES.put("[OR r32, [r64]]", "0b [00-3f] [SIB?]");
TEMPLATES.put("[OR r64, [r64]]", "4[8-f] 0b [00-3f] [SIB?]");
// --- OR: Memory (RIP-Relative) ← Register ---
TEMPLATES.put("[OR [rip+off32], r8]", "08 0d ? ? ? ?");
TEMPLATES.put("[OR [rip+off32], r32]", "09 0d ? ? ? ?");
TEMPLATES.put("[OR [rip+off32], r64]", "4[8-f] 09 0d ? ? ? ?");
// --- OR: Memory (r64 base + disp32) ← Register ---
TEMPLATES.put("[OR [r64+off32], r8]", "08 [88-8f] [SIB?] ? ? ? ?");
TEMPLATES.put("[OR [r64+off32], r32]", "09 [88-8f] [SIB?] ? ? ? ?");
TEMPLATES.put("[OR [r64+off32], r64]", "4[8-f] 09 [88-8f] [SIB?] ? ? ? ?");
// --- OR: Memory (r64 base + disp8) ← Register ---
TEMPLATES.put("[OR [r64+off8], r8]", "08 [48-4f] [SIB?] ?");
TEMPLATES.put("[OR [r64+off8], r32]", "09 [48-4f] [SIB?] ?");
TEMPLATES.put("[OR [r64+off8], r64]", "4[8-f] 09 [48-4f] [SIB?] ?");
// --- OR: Memory (r64 base, no displacement) ← Register ---
TEMPLATES.put("[OR [r64], r8]", "08 [08-0f] [SIB?]");
TEMPLATES.put("[OR [r64], r32]", "09 [08-0f] [SIB?]");
TEMPLATES.put("[OR [r64], r64]", "4[8-f] 09 [08-0f] [SIB?]");
// --- OR: Memory (r64 base + disp32) ← Immediate ---
TEMPLATES.put("[OR byte ptr [r64+off32], imm8]", "80 [88-8f] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[OR dword ptr [r64+off32], imm32]", "81 [88-8f] [SIB?] ? ? ? ? ? ? ? ?");
TEMPLATES.put("[OR qword ptr [r64+off32], imm64_32]", "4[8-f] 81 [88-8f] [SIB?] ? ? ? ? ? ? ? ?");
// --- OR: Memory (r64 base + disp8) ← Immediate ---
TEMPLATES.put("[OR byte ptr [r64+off8], imm8]", "80 [48-4f] [SIB?] ? ?");
TEMPLATES.put("[OR dword ptr [r64+off8], imm32]", "81 [48-4f] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[OR qword ptr [r64+off8], imm64_32]", "4[8-f] 81 [48-4f] [SIB?] ? ? ? ? ?");
// --- OR: Memory (RIP-Relative) ← Immediate ---
TEMPLATES.put("[OR byte ptr [rip+off32], imm8]", "80 0d ? ? ? ? ?");
TEMPLATES.put("[OR dword ptr [rip+off32], imm32]", "81 0d ? ? ? ? ? ? ? ?");
TEMPLATES.put("[OR qword ptr [rip+off32], imm64_32]", "4[8-f] 81 0d ? ? ? ? ? ? ? ?");
// --- OR: SIB-specific Load (ModRM R/M=100, register ← memory) ---
TEMPLATES.put("[OR r8, [r64+sib+off32]]", "0a [84-bc] ? ? ? ? ?");
TEMPLATES.put("[OR r8, [r64+sib+off8]]", "0a [44-7c] ? ? ?");
TEMPLATES.put("[OR r8, [r64+sib]]", "0a [04-3c] ?");
TEMPLATES.put("[OR r32, [r64+sib+off32]]", "0b [84-bc] ? ? ? ? ?");
TEMPLATES.put("[OR r32, [r64+sib+off8]]", "0b [44-7c] ? ? ?");
TEMPLATES.put("[OR r32, [r64+sib]]", "0b [04-3c] ?");
TEMPLATES.put("[OR r64, [r64+sib+off32]]", "4[8-f] 0b [84-bc] ? ? ? ? ?");
TEMPLATES.put("[OR r64, [r64+sib+off8]]", "4[8-f] 0b [44-7c] ? ? ?");
TEMPLATES.put("[OR r64, [r64+sib]]", "4[8-f] 0b [04-3c] ?");
// --- OR: SIB-specific Store (ModRM R/M=100, memory ← register) ---
TEMPLATES.put("[OR [r64+sib+off32], r8]", "08 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[OR [r64+sib+off8], r8]", "08 [44-7c] ? ? ?");
TEMPLATES.put("[OR [r64+sib], r8]", "08 [04-3c] ?");
TEMPLATES.put("[OR [r64+sib+off32], r32]", "09 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[OR [r64+sib+off8], r32]", "09 [44-7c] ? ? ?");
TEMPLATES.put("[OR [r64+sib], r32]", "09 [04-3c] ?");
TEMPLATES.put("[OR [r64+sib+off32], r64]", "4[8-f] 09 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[OR [r64+sib+off8], r64]", "4[8-f] 09 [44-7c] ? ? ?");
TEMPLATES.put("[OR [r64+sib], r64]", "4[8-f] 09 [04-3c] ?");
// --- INC / DEC Instructions ---
TEMPLATES.put("[INC r64]", "4[8-f] ff [c0-c7]");
TEMPLATES.put("[INC r32]", "ff [c0-c7]");
TEMPLATES.put("[DEC r64]", "4[8-f] ff [c8-cf]");
TEMPLATES.put("[DEC r32]", "ff [c8-cf]");
// --- NOT Instructions ---
TEMPLATES.put("[NOT r64]", "4[8-f] f7 [d0-d7]");
TEMPLATES.put("[NOT r32]", "f7 [d0-d7]");
// --- TEST Instructions ---
TEMPLATES.put("[TEST r64, r64]", "4[8-f] 85 [c0-ff]");
TEMPLATES.put("[TEST r32, r32]", "85 [c0-ff]");
TEMPLATES.put("[TEST r8, r8]", "84 [c0-ff]");
// --- SHIFT by Immediate (Group 2, opcode C1) ---
TEMPLATES.put("[SHL r32, imm8]", "c1 [e0-e7] ?");
TEMPLATES.put("[SHL r64, imm8]", "4[8-f] c1 [e0-e7] ?");
TEMPLATES.put("[SHR r32, imm8]", "c1 [e8-ef] ?");
TEMPLATES.put("[SHR r64, imm8]", "4[8-f] c1 [e8-ef] ?");
TEMPLATES.put("[SAR r32, imm8]", "c1 [f8-ff] ?");
TEMPLATES.put("[SAR r64, imm8]", "4[8-f] c1 [f8-ff] ?");
// =========================================================================
// === COMPARISONS (CMP) ===
// =========================================================================
// --- CMP: Register ← Register ---
TEMPLATES.put("[CMP r64, r64]", "4[8-f] 3[9|b] [c0-ff]");
TEMPLATES.put("[CMP r32, r32]", "3[9|b] [c0-ff]");
TEMPLATES.put("[CMP r16, r16]", "66 3[9|b] [c0-ff]");
TEMPLATES.put("[CMP r8, r8]", "3[8|a] [c0-ff]");
// --- CMP: Register ← Immediate ---
TEMPLATES.put("[CMP r64, imm32]", "4[8-f] 81 [f8-ff] ? ? ? ?");
TEMPLATES.put("[CMP r32, imm32]", "81 [f8-ff] ? ? ? ?");
TEMPLATES.put("[CMP r16, imm16]", "66 81 [f8-ff] ? ?");
TEMPLATES.put("[CMP r8, imm8]", "80 [f8-ff] ?");
TEMPLATES.put("[CMP r64, imm8]", "4[8-f] 83 [f8-ff] ?");
TEMPLATES.put("[CMP r32, imm8]", "83 [f8-ff] ?");
TEMPLATES.put("[CMP r16, imm8]", "66 83 [f8-ff] ?");
// --- CMP: Register ← Memory (RIP-Relative) ---
TEMPLATES.put("[CMP r8, [rip+off32]]", "3a 3d ? ? ? ?");
TEMPLATES.put("[CMP r32, [rip+off32]]", "3b 3d ? ? ? ?");
TEMPLATES.put("[CMP r64, [rip+off32]]", "4[8-f] 3b 3d ? ? ? ?");
TEMPLATES.put("[CMP r16, [rip+off32]]", "66 3b 3d ? ? ? ?");
// --- CMP: Register ← Memory (r64 base + disp32) ---
TEMPLATES.put("[CMP r8, [r64+off32]]", "3a [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[CMP r32, [r64+off32]]", "3b [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[CMP r64, [r64+off32]]", "4[8-f] 3b [80-bf] [SIB?] ? ? ? ?");
// --- CMP: Register ← Memory (r64 base + disp8) ---
TEMPLATES.put("[CMP r8, [r64+off8]]", "3a [40-7f] [SIB?] ?");
TEMPLATES.put("[CMP r32, [r64+off8]]", "3b [40-7f] [SIB?] ?");
TEMPLATES.put("[CMP r64, [r64+off8]]", "4[8-f] 3b [40-7f] [SIB?] ?");
// --- CMP: Register ← Memory (r64 base, no displacement) ---
TEMPLATES.put("[CMP r8, [r64]]", "3a [00-3f] [SIB?]");
TEMPLATES.put("[CMP r32, [r64]]", "3b [00-3f] [SIB?]");
TEMPLATES.put("[CMP r64, [r64]]", "4[8-f] 3b [00-3f] [SIB?]");
// --- CMP: Memory (RIP-Relative) ← Register ---
TEMPLATES.put("[CMP [rip+off32], r8]", "38 3d ? ? ? ?");
TEMPLATES.put("[CMP [rip+off32], r32]", "39 3d ? ? ? ?");
TEMPLATES.put("[CMP [rip+off32], r64]", "4[8-f] 39 3d ? ? ? ?");
TEMPLATES.put("[CMP [rip+off32], r16]", "66 39 3d ? ? ? ?");
// --- CMP: Memory (r64 base + disp32) ← Register ---
TEMPLATES.put("[CMP [r64+off32], r8]", "38 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[CMP [r64+off32], r32]", "39 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[CMP [r64+off32], r64]", "4[8-f] 39 [80-bf] [SIB?] ? ? ? ?");
// --- CMP: Memory (r64 base + disp8) ← Register ---
TEMPLATES.put("[CMP [r64+off8], r8]", "38 [40-7f] [SIB?] ?");
TEMPLATES.put("[CMP [r64+off8], r32]", "39 [40-7f] [SIB?] ?");
TEMPLATES.put("[CMP [r64+off8], r64]", "4[8-f] 39 [40-7f] [SIB?] ?");
// --- CMP: Memory (r64 base, no displacement) ← Register ---
TEMPLATES.put("[CMP [r64], r8]", "38 [00-3f] [SIB?]");
TEMPLATES.put("[CMP [r64], r32]", "39 [00-3f] [SIB?]");
TEMPLATES.put("[CMP [r64], r64]", "4[8-f] 39 [00-3f] [SIB?]");
// --- CMP: Memory (r64 base + disp32) ← Immediate ---
TEMPLATES.put("[CMP byte ptr [r64+off32], imm8]", "80 [b8-bf] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[CMP dword ptr [r64+off32], imm32]", "81 [b8-bf] [SIB?] ? ? ? ? ? ? ? ?");
TEMPLATES.put("[CMP qword ptr [r64+off32], imm64_32]", "4[8-f] 81 [b8-bf] [SIB?] ? ? ? ? ? ? ? ?");
// --- CMP: Memory (r64 base + disp8) ← Immediate ---
TEMPLATES.put("[CMP byte ptr [r64+off8], imm8]", "80 [78-7f] [SIB?] ? ?");
TEMPLATES.put("[CMP dword ptr [r64+off8], imm32]", "81 [78-7f] [SIB?] ? ? ? ? ?");
TEMPLATES.put("[CMP qword ptr [r64+off8], imm64_32]", "4[8-f] 81 [78-7f] [SIB?] ? ? ? ? ?");
// --- CMP: Memory (RIP-Relative) ← Immediate ---
TEMPLATES.put("[CMP byte ptr [rip+off32], imm8]", "80 3d ? ? ? ? ?");
TEMPLATES.put("[CMP dword ptr [rip+off32], imm32]", "81 3d ? ? ? ? ? ? ? ?");
TEMPLATES.put("[CMP qword ptr [rip+off32], imm64_32]", "4[8-f] 81 3d ? ? ? ? ? ? ? ?");
// --- CMP: SIB-specific Load (ModRM R/M=100, register ← memory) ---
TEMPLATES.put("[CMP r8, [r64+sib+off32]]", "3a [84-bc] ? ? ? ? ?");
TEMPLATES.put("[CMP r8, [r64+sib+off8]]", "3a [44-7c] ? ? ?");
TEMPLATES.put("[CMP r8, [r64+sib]]", "3a [04-3c] ?");
TEMPLATES.put("[CMP r32, [r64+sib+off32]]", "3b [84-bc] ? ? ? ? ?");
TEMPLATES.put("[CMP r32, [r64+sib+off8]]", "3b [44-7c] ? ? ?");
TEMPLATES.put("[CMP r32, [r64+sib]]", "3b [04-3c] ?");
TEMPLATES.put("[CMP r64, [r64+sib+off32]]", "4[8-f] 3b [84-bc] ? ? ? ? ?");
TEMPLATES.put("[CMP r64, [r64+sib+off8]]", "4[8-f] 3b [44-7c] ? ? ?");
TEMPLATES.put("[CMP r64, [r64+sib]]", "4[8-f] 3b [04-3c] ?");
// --- CMP: SIB-specific Store (ModRM R/M=100, memory ← register) ---
TEMPLATES.put("[CMP [r64+sib+off32], r8]", "38 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[CMP [r64+sib+off8], r8]", "38 [44-7c] ? ? ?");
TEMPLATES.put("[CMP [r64+sib], r8]", "38 [04-3c] ?");
TEMPLATES.put("[CMP [r64+sib+off32], r32]", "39 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[CMP [r64+sib+off8], r32]", "39 [44-7c] ? ? ?");
TEMPLATES.put("[CMP [r64+sib], r32]", "39 [04-3c] ?");
TEMPLATES.put("[CMP [r64+sib+off32], r64]", "4[8-f] 39 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[CMP [r64+sib+off8], r64]", "4[8-f] 39 [44-7c] ? ? ?");
TEMPLATES.put("[CMP [r64+sib], r64]", "4[8-f] 39 [04-3c] ?");
// =========================================================================
// === CONDITIONAL MOVES (CMOV) ===
// =========================================================================
// --- CMOV: Register ← Register (32-bit and 64-bit) ---
TEMPLATES.put("[CMOVO r64, r64]", "4[8-f] 0f 40 [c0-ff]");
TEMPLATES.put("[CMOVNO r64, r64]", "4[8-f] 0f 41 [c0-ff]");
TEMPLATES.put("[CMOVB r64, r64]", "4[8-f] 0f 42 [c0-ff]");
TEMPLATES.put("[CMOVNB r64, r64]", "4[8-f] 0f 43 [c0-ff]");
TEMPLATES.put("[CMOVE r64, r64]", "4[8-f] 0f 44 [c0-ff]");
TEMPLATES.put("[CMOVNE r64, r64]", "4[8-f] 0f 45 [c0-ff]");
TEMPLATES.put("[CMOVBE r64, r64]", "4[8-f] 0f 46 [c0-ff]");
TEMPLATES.put("[CMOVA r64, r64]", "4[8-f] 0f 47 [c0-ff]");
TEMPLATES.put("[CMOVS r64, r64]", "4[8-f] 0f 48 [c0-ff]");
TEMPLATES.put("[CMOVNS r64, r64]", "4[8-f] 0f 49 [c0-ff]");
TEMPLATES.put("[CMOVP r64, r64]", "4[8-f] 0f 4a [c0-ff]");
TEMPLATES.put("[CMOVNP r64, r64]", "4[8-f] 0f 4b [c0-ff]");
TEMPLATES.put("[CMOVL r64, r64]", "4[8-f] 0f 4c [c0-ff]");
TEMPLATES.put("[CMOVGE r64, r64]", "4[8-f] 0f 4d [c0-ff]");
TEMPLATES.put("[CMOVLE r64, r64]", "4[8-f] 0f 4e [c0-ff]");
TEMPLATES.put("[CMOVG r64, r64]", "4[8-f] 0f 4f [c0-ff]");
TEMPLATES.put("[CMOVO r32, r32]", "0f 40 [c0-ff]");
TEMPLATES.put("[CMOVNO r32, r32]", "0f 41 [c0-ff]");
TEMPLATES.put("[CMOVB r32, r32]", "0f 42 [c0-ff]");
TEMPLATES.put("[CMOVNB r32, r32]", "0f 43 [c0-ff]");
TEMPLATES.put("[CMOVE r32, r32]", "0f 44 [c0-ff]");
TEMPLATES.put("[CMOVNE r32, r32]", "0f 45 [c0-ff]");
TEMPLATES.put("[CMOVBE r32, r32]", "0f 46 [c0-ff]");
TEMPLATES.put("[CMOVA r32, r32]", "0f 47 [c0-ff]");
TEMPLATES.put("[CMOVS r32, r32]", "0f 48 [c0-ff]");
TEMPLATES.put("[CMOVNS r32, r32]", "0f 49 [c0-ff]");
TEMPLATES.put("[CMOVP r32, r32]", "0f 4a [c0-ff]");
TEMPLATES.put("[CMOVNP r32, r32]", "0f 4b [c0-ff]");
TEMPLATES.put("[CMOVL r32, r32]", "0f 4c [c0-ff]");
TEMPLATES.put("[CMOVGE r32, r32]", "0f 4d [c0-ff]");
TEMPLATES.put("[CMOVLE r32, r32]", "0f 4e [c0-ff]");
TEMPLATES.put("[CMOVG r32, r32]", "0f 4f [c0-ff]");
// --- CMOV: Register ← Memory (generic addressing) ---
TEMPLATES.put("[CMOVcc r64, [r64+off32]]", "4[8-f] 0f 4[0-f] [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[CMOVcc r64, [r64+off8]]", "4[8-f] 0f 4[0-f] [40-7f] [SIB?] ?");
TEMPLATES.put("[CMOVcc r64, [r64]]", "4[8-f] 0f 4[0-f] [00-3f] [SIB?]");
TEMPLATES.put("[CMOVcc r64, [rip+off32]]", "4[8-f] 0f 4[0-f] [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[CMOVcc r32, [r64+off32]]", "0f 4[0-f] [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[CMOVcc r32, [r64+off8]]", "0f 4[0-f] [40-7f] [SIB?] ?");
TEMPLATES.put("[CMOVcc r32, [r64]]", "0f 4[0-f] [00-3f] [SIB?]");
TEMPLATES.put("[CMOVcc r32, [rip+off32]]", "0f 4[0-f] [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
// --- CMOV: SIB-specific Load (ModRM R/M=100, register ← memory) ---
TEMPLATES.put("[CMOVcc r64, [r64+sib+off32]]", "4[8-f] 0f 4[0-f] [84-bc] ? ? ? ? ?");
TEMPLATES.put("[CMOVcc r64, [r64+sib+off8]]", "4[8-f] 0f 4[0-f] [44-7c] ? ? ?");
TEMPLATES.put("[CMOVcc r64, [r64+sib]]", "4[8-f] 0f 4[0-f] [04-3c] ?");
TEMPLATES.put("[CMOVcc r32, [r64+sib+off32]]", "0f 4[0-f] [84-bc] ? ? ? ? ?");
TEMPLATES.put("[CMOVcc r32, [r64+sib+off8]]", "0f 4[0-f] [44-7c] ? ? ?");
TEMPLATES.put("[CMOVcc r32, [r64+sib]]", "0f 4[0-f] [04-3c] ?");
// =========================================================================
// === CALL / RET / LEAVE / JMP / Jcc ===
// =========================================================================
// --- CALL ---
TEMPLATES.put("[CALL rel32]", "e8 ? ? ? ?");
TEMPLATES.put("[CALL r64]", "ff [d0-d7]");
TEMPLATES.put("[CALL r32]", "ff [d0-d7]");
TEMPLATES.put("[CALL [r64+off32]]", "ff [90-97] [SIB?] ? ? ? ?");
TEMPLATES.put("[CALL [r64+off8]]", "ff [50-57] [SIB?] ?");
TEMPLATES.put("[CALL [r64]]", "ff [10-17] [SIB?]");
TEMPLATES.put("[CALL [rip+off32]]", "ff 15 ? ? ? ?");
TEMPLATES.put("[CALL [rip+sib+off32]]", "ff 14 25 ? ? ? ?");
// --- CALL: SIB-specific ---
TEMPLATES.put("[CALL [r64+sib+off32]]", "ff 94 ? ? ? ? ?");
TEMPLATES.put("[CALL [r64+sib+off8]]", "ff 54 ? ? ?");
TEMPLATES.put("[CALL [r64+sib]]", "ff 14 ? ?");
// --- RET / LEAVE ---
TEMPLATES.put("[RET]", "c3");
TEMPLATES.put("[RET imm16]", "c2 ? ?");
TEMPLATES.put("[LEAVE]", "c9");
// --- JMP ---
TEMPLATES.put("[JMP rel32]", "e9 ? ? ? ?");
TEMPLATES.put("[JMP rel8]", "eb ?");
TEMPLATES.put("[JMP r64]", "ff [e0-e7]");
TEMPLATES.put("[JMP r32]", "ff [e0-e7]");
TEMPLATES.put("[JMP [r64+off32]]", "ff [a0-a7] [SIB?] ? ? ? ?");
TEMPLATES.put("[JMP [r64+off8]]", "ff [60-67] [SIB?] ?");
TEMPLATES.put("[JMP [r64]]", "ff [20-27] [SIB?]");
TEMPLATES.put("[JMP [rip+off32]]", "ff 25 ? ? ? ?");
TEMPLATES.put("[JMP [rip+sib+off32]]", "ff 24 25 ? ? ? ?");
// --- JMP: SIB-specific ---
TEMPLATES.put("[JMP [r64+sib+off32]]", "ff a4 ? ? ? ? ?");
TEMPLATES.put("[JMP [r64+sib+off8]]", "ff 64 ? ? ?");
TEMPLATES.put("[JMP [r64+sib]]", "ff 24 ? ?");
// --- Jcc rel32 ---
TEMPLATES.put("[JO rel32]", "0f 80 ? ? ? ?");
TEMPLATES.put("[JNO rel32]", "0f 81 ? ? ? ?");
TEMPLATES.put("[JB rel32]", "0f 82 ? ? ? ?");
TEMPLATES.put("[JAE rel32]", "0f 83 ? ? ? ?");
TEMPLATES.put("[JE rel32]", "0f 84 ? ? ? ?");
TEMPLATES.put("[JNE rel32]", "0f 85 ? ? ? ?");
TEMPLATES.put("[JBE rel32]", "0f 86 ? ? ? ?");
TEMPLATES.put("[JA rel32]", "0f 87 ? ? ? ?");
TEMPLATES.put("[JS rel32]", "0f 88 ? ? ? ?");
TEMPLATES.put("[JNS rel32]", "0f 89 ? ? ? ?");
TEMPLATES.put("[JP rel32]", "0f 8a ? ? ? ?");
TEMPLATES.put("[JNP rel32]", "0f 8b ? ? ? ?");
TEMPLATES.put("[JL rel32]", "0f 8c ? ? ? ?");
TEMPLATES.put("[JGE rel32]", "0f 8d ? ? ? ?");
TEMPLATES.put("[JLE rel32]", "0f 8e ? ? ? ?");
TEMPLATES.put("[JG rel32]", "0f 8f ? ? ? ?");
// --- Jcc rel8 ---
TEMPLATES.put("[JO rel8]", "70 ?");
TEMPLATES.put("[JNO rel8]", "71 ?");
TEMPLATES.put("[JB rel8]", "72 ?");
TEMPLATES.put("[JAE rel8]", "73 ?");
TEMPLATES.put("[JE rel8]", "74 ?");
TEMPLATES.put("[JNE rel8]", "75 ?");
TEMPLATES.put("[JBE rel8]", "76 ?");
TEMPLATES.put("[JA rel8]", "77 ?");
TEMPLATES.put("[JS rel8]", "78 ?");
TEMPLATES.put("[JNS rel8]", "79 ?");
TEMPLATES.put("[JP rel8]", "7a ?");
TEMPLATES.put("[JNP rel8]", "7b ?");
TEMPLATES.put("[JL rel8]", "7c ?");
TEMPLATES.put("[JGE rel8]", "7d ?");
TEMPLATES.put("[JLE rel8]", "7e ?");
TEMPLATES.put("[JG rel8]", "7f ?");
// =========================================================================
// === XMM / FLOATING-POINT ===
// =========================================================================
// --- MOVSS: Scalar Single-Precision (load) ---
TEMPLATES.put("[MOVSS xmm, [rip+off32]]", "f3 0f 10 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVSS xmm, [r64+off32]]", "f3 0f 10 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVSS xmm, [r64+off8]]", "f3 0f 10 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSS xmm, [r64]]", "f3 0f 10 [00-3f] [SIB?]");
TEMPLATES.put("[MOVSS xmm, xmm]", "f3 0f 10 [c0-ff]");
// --- MOVSS: Scalar Single-Precision (store) ---
TEMPLATES.put("[MOVSS [rip+off32], xmm]", "f3 0f 11 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVSS [r64+off32], xmm]", "f3 0f 11 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVSS [r64+off8], xmm]", "f3 0f 11 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSS [r64], xmm]", "f3 0f 11 [00-3f] [SIB?]");
// --- MOVSD: Scalar Double-Precision (load) ---
TEMPLATES.put("[MOVSD xmm, [rip+off32]]", "f2 0f 10 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVSD xmm, [r64+off32]]", "f2 0f 10 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVSD xmm, [r64+off8]]", "f2 0f 10 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSD xmm, [r64]]", "f2 0f 10 [00-3f] [SIB?]");
TEMPLATES.put("[MOVSD xmm, xmm]", "f2 0f 10 [c0-ff]");
// --- MOVSD: Scalar Double-Precision (store) ---
TEMPLATES.put("[MOVSD [rip+off32], xmm]", "f2 0f 11 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVSD [r64+off32], xmm]", "f2 0f 11 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVSD [r64+off8], xmm]", "f2 0f 11 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVSD [r64], xmm]", "f2 0f 11 [00-3f] [SIB?]");
// --- MOVSS/MOVSD: SIB-specific load ---
TEMPLATES.put("[MOVSS xmm, [r64+sib+off32]]", "f3 0f 10 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOVSS xmm, [r64+sib+off8]]", "f3 0f 10 [44-7c] ? ? ?");
TEMPLATES.put("[MOVSS xmm, [r64+sib]]", "f3 0f 10 [04-3c] ?");
TEMPLATES.put("[MOVSD xmm, [r64+sib+off32]]", "f2 0f 10 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOVSD xmm, [r64+sib+off8]]", "f2 0f 10 [44-7c] ? ? ?");
TEMPLATES.put("[MOVSD xmm, [r64+sib]]", "f2 0f 10 [04-3c] ?");
// --- MOVSS/MOVSD: SIB-specific store ---
TEMPLATES.put("[MOVSS [r64+sib+off32], xmm]", "f3 0f 11 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOVSS [r64+sib+off8], xmm]", "f3 0f 11 [44-7c] ? ? ?");
TEMPLATES.put("[MOVSS [r64+sib], xmm]", "f3 0f 11 [04-3c] ?");
TEMPLATES.put("[MOVSD [r64+sib+off32], xmm]", "f2 0f 11 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOVSD [r64+sib+off8], xmm]", "f2 0f 11 [44-7c] ? ? ?");
TEMPLATES.put("[MOVSD [r64+sib], xmm]", "f2 0f 11 [04-3c] ?");
// --- MOVUPS: Unaligned Packed Single (load) ---
TEMPLATES.put("[MOVUPS xmm, [rip+off32]]", "0f 10 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVUPS xmm, [r64+off32]]", "0f 10 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVUPS xmm, [r64+off8]]", "0f 10 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVUPS xmm, [r64]]", "0f 10 [00-3f] [SIB?]");
// --- MOVUPS: Unaligned Packed Single (store) ---
TEMPLATES.put("[MOVUPS [rip+off32], xmm]", "0f 11 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVUPS [r64+off32], xmm]", "0f 11 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVUPS [r64+off8], xmm]", "0f 11 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVUPS [r64], xmm]", "0f 11 [00-3f] [SIB?]");
// --- MOVUPD: Unaligned Packed Double (load) ---
TEMPLATES.put("[MOVUPD xmm, [rip+off32]]", "66 0f 10 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVUPD xmm, [r64+off32]]", "66 0f 10 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVUPD xmm, [r64+off8]]", "66 0f 10 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVUPD xmm, [r64]]", "66 0f 10 [00-3f] [SIB?]");
// --- MOVUPD: Unaligned Packed Double (store) ---
TEMPLATES.put("[MOVUPD [rip+off32], xmm]", "66 0f 11 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVUPD [r64+off32], xmm]", "66 0f 11 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVUPD [r64+off8], xmm]", "66 0f 11 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVUPD [r64], xmm]", "66 0f 11 [00-3f] [SIB?]");
// --- MOVAPS: Aligned Packed Single (load) ---
TEMPLATES.put("[MOVAPS xmm, [rip+off32]]", "0f 28 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVAPS xmm, [r64+off32]]", "0f 28 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVAPS xmm, [r64+off8]]", "0f 28 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVAPS xmm, [r64]]", "0f 28 [00-3f] [SIB?]");
// --- MOVAPS: Aligned Packed Single (store) ---
TEMPLATES.put("[MOVAPS [rip+off32], xmm]", "0f 29 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVAPS [r64+off32], xmm]", "0f 29 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVAPS [r64+off8], xmm]", "0f 29 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVAPS [r64], xmm]", "0f 29 [00-3f] [SIB?]");
// --- MOVAPS: SIB-specific ---
TEMPLATES.put("[MOVAPS xmm, [r64+sib+off32]]", "0f 28 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOVAPS xmm, [r64+sib+off8]]", "0f 28 [44-7c] ? ? ?");
TEMPLATES.put("[MOVAPS xmm, [r64+sib]]", "0f 28 [04-3c] ?");
TEMPLATES.put("[MOVAPS [r64+sib+off32], xmm]", "0f 29 [84-bc] ? ? ? ? ?");
TEMPLATES.put("[MOVAPS [r64+sib+off8], xmm]", "0f 29 [44-7c] ? ? ?");
TEMPLATES.put("[MOVAPS [r64+sib], xmm]", "0f 29 [04-3c] ?");
// --- MOVAPD: Aligned Packed Double (load) ---
TEMPLATES.put("[MOVAPD xmm, [rip+off32]]", "66 0f 28 [05|0d|15|1d|25|2d|35|3d] ? ? ? ?");
TEMPLATES.put("[MOVAPD xmm, [r64+off32]]", "66 0f 28 [80-bf] [SIB?] ? ? ? ?");
TEMPLATES.put("[MOVAPD xmm, [r64+off8]]", "66 0f 28 [40-7f] [SIB?] ?");
TEMPLATES.put("[MOVAPD xmm, [r64]]", "66 0f 28 [00-3f] [SIB?]");
// --- MOVAPD: Aligned Packed Double (store) ---