From 6eb80dc31e75d2690235a4e9fba71e4771542de2 Mon Sep 17 00:00:00 2001
From: Jeremy Lau <30300826+fdxmw@users.noreply.github.com>
Date: Fri, 31 Jul 2026 08:22:24 -0700
Subject: [PATCH 1/2] Disable the `deploy-pages` action when running outside of
 UCSBarchlab/development.

This prevents forks from publishing more copies of the website.
---
 .github/workflows/pages-deploy.yml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.github/workflows/pages-deploy.yml b/.github/workflows/pages-deploy.yml
index 81d27e87..5e8d93bd 100644
--- a/.github/workflows/pages-deploy.yml
+++ b/.github/workflows/pages-deploy.yml
@@ -22,6 +22,8 @@ jobs:
         path: www/_build/html
 
   deploy:
+    # Only deploy for UCSBarchlab/PyRTL.
+    if: ${{ github.repository == 'UCSBarchlab/PyRTL' && github.ref_name == 'development' }}
     needs: build
     permissions:
       pages: write

From 8b05d649190e5e75a9ba946634b52a34ffea5211 Mon Sep 17 00:00:00 2001
From: Jeremy Lau <30300826+fdxmw@users.noreply.github.com>
Date: Fri, 31 Jul 2026 08:31:23 -0700
Subject: [PATCH 2/2] Update related projects link in README.md and minor
 website edits.

---
 README.md     |  2 +-
 www/index.rst | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/README.md b/README.md
index e274763f..1d5794f7 100644
--- a/README.md
+++ b/README.md
@@ -200,4 +200,4 @@ It is always important to point out that PyRTL builds on the ideas of several
 other related projects as we all share the common goal of trying to make
 hardware design a better experience! You can read more about those
 relationships on our [PyRTL project web
-page](http://ucsbarchlab.github.io/PyRTL/).
+page](https://pyrtl.readthedocs.io/en/latest/#related-projects)
diff --git a/www/index.rst b/www/index.rst
index 651fd648..34f96830 100644
--- a/www/index.rst
+++ b/www/index.rst
@@ -221,8 +221,8 @@ Notebooks on any of our examples on MyBinder
 Hello N-bit Ripple-Carry Adder!
 ===============================
 
-While adders are a builtin primitive for PyRTL, most people doing RTL are
-familiar with the idea of a `Ripple-Carry Adder
+While adders are a builtin primitive for PyRTL, most people writing RTL are
+familiar with `Ripple-Carry Adders
 <https://en.wikipedia.org/wiki/Adder_(electronics)>`_ and so it is useful to
 see how you might express one in PyRTL. Rather than the typical `Verilog
 introduction to fixed 4-bit adders
@@ -235,9 +235,9 @@ The code above includes ``ripple_add``, an adder generator with Python-style
 slices on wires, ``counter``, an instance of :class:`~pyrtl.Register`, and all
 the code needed to simulate the design, generate a waveform, and render it to
 the terminal. `Example 2
-<https://github.com/UCSBarchlab/PyRTL/blob/development/examples/example2-counter.py>`_'s
-comments describe this code in much more detail. Running this code shows a
-counter running from 0 to 7 and repeating:
+<https://github.com/UCSBarchlab/PyRTL/blob/development/examples/example2-counter.py>`_
+has more comments on how this code works. Running this code shows a counter
+running from 0 to 7 and repeating:
 
 .. image:: ../docs/screenshots/ripple-carry.png
    :width: 34em