diff --git a/.gitignore b/.gitignore
index 877bb3f222..73e750178e 100644
--- a/.gitignore
+++ b/.gitignore
@@ -15,4 +15,10 @@ gpu-simulator/accel_sim.pyi
 compile_commands.json
 .cache
 .cursorrules
-CLAUDE.md
\ No newline at end of file
+.cursor
+CLAUDE.md
+tutorial
+# RTX3060 bring-up working artifacts (not for PR)
+util/tuner/stats.txt
+util/tuner/gpu-app-collection-partial/
+util/plotting/correl-html/
diff --git a/gpu-simulator/configs/tested-cfgs/SM86_RTX3060_MOBILE/trace.config b/gpu-simulator/configs/tested-cfgs/SM86_RTX3060_MOBILE/trace.config
new file mode 100644
index 0000000000..5807e54210
--- /dev/null
+++ b/gpu-simulator/configs/tested-cfgs/SM86_RTX3060_MOBILE/trace.config
@@ -0,0 +1,22 @@
+-trace_opcode_latency_initiation_int 4,2
+-trace_opcode_latency_initiation_sp 4,2
+-trace_opcode_latency_initiation_dp 64,64
+-trace_opcode_latency_initiation_sfu 23,8
+-trace_opcode_latency_initiation_tensor 32,32
+
+#execute branch insts on spec unit 1
+#<enabled>,<num_units>,<max_latency>,<ID_OC_SPEC>,<OC_EX_SPEC>,<NAME>
+-specialized_unit_1 1,4,4,4,4,BRA
+-trace_opcode_latency_initiation_spec_op_1 4,4
+
+#TEX unit, make fixed latency for all tex insts
+-specialized_unit_2 1,4,200,4,4,TEX
+-trace_opcode_latency_initiation_spec_op_2 200,4
+
+#tensor unit
+-specialized_unit_3 1,4,32,4,4,TENSOR
+-trace_opcode_latency_initiation_spec_op_3 32,32
+
+#UDP unit, for turing and above
+-specialized_unit_4 1,4,4,4,4,UDP
+-trace_opcode_latency_initiation_spec_op_4 4,1
diff --git a/util/job_launching/configs/define-standard-cfgs.yml b/util/job_launching/configs/define-standard-cfgs.yml
index 46c0d04b4d..ae453ff835 100644
--- a/util/job_launching/configs/define-standard-cfgs.yml
+++ b/util/job_launching/configs/define-standard-cfgs.yml
@@ -15,6 +15,10 @@ TITANK:
 RTX3070:
     base_file: "$GPGPUSIM_ROOT/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config"
 
+#Ampere RTX 3060 Laptop
+RTX3060M:
+    base_file: "$GPGPUSIM_ROOT/configs/tested-cfgs/SM86_RTX3060_MOBILE/gpgpusim.config"
+
 #Turing
 RTX2060:
     base_file: "$GPGPUSIM_ROOT/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config"
diff --git a/util/job_launching/stats/example_stats.yml b/util/job_launching/stats/example_stats.yml
index ee320e12de..f7821d6633 100644
--- a/util/job_launching/stats/example_stats.yml
+++ b/util/job_launching/stats/example_stats.yml
@@ -14,7 +14,17 @@ collect_aggregate:
     - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_R\]\[HIT\]\s*=\s*(.*)'
     - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_R\]\[TOTAL_ACCESS\]\s*=\s*(.*)'
     - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)'
+    - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)'
     - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)'
+    # Local-memory writes also traverse L1 -> L2, and NVIDIA's
+    # lts__t_sectors_srcunit_tex_op_write* counters are all-source, so the L2 write
+    # correlations must add these. Collected as HIT/MISS/SECTOR_MISS rather than
+    # TOTAL_ACCESS because GPGPU-Sim only emits a TOTAL_ACCESS line for access types
+    # with non-zero traffic, whereas these three are always printed (as 0).
+    - '\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)'
+    - '\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[MISS\]\s*=\s*(.*)'
+    - '\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[SECTOR_MISS\]\s*=\s*(.*)'
+    - '\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)'
     - '\s+Total_core_cache_stats_breakdown\[GLOBAL_ACC_R\]\[TOTAL_ACCESS\]\s*=\s*(.*)'
     - '\s+Total_core_cache_stats_breakdown\[GLOBAL_ACC_R\]\[HIT\]\s*=\s*(.*)'
     - '\s+Total_core_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)'
diff --git a/util/plotting/correl_mappings.py b/util/plotting/correl_mappings.py
index 671b8bc101..6433150f69 100644
--- a/util/plotting/correl_mappings.py
+++ b/util/plotting/correl_mappings.py
@@ -12,6 +12,7 @@
     "GV100": set("Quadro GV100"),
     "RTX2060": set("GeForce RTX 2060"),
     "RTX3070": set("GeForce RTX 3070"),
+    "RTX3060M": set(["NVIDIA GeForce RTX 3060 Laptop GPU"]),
     "A100": set("NVIDIA A100 80GB"),
     "H100" : set("NVIDIA H100 80GB HBM3"),
 }
@@ -406,7 +407,10 @@
         plotfile="l2-write-transactions",
         hw_eval='np.average(hw["lts__t_sectors_srcunit_tex_op_write.sum"])',
         hw_error=None,
-        sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])',
+        sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[MISS\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[SECTOR_MISS\]\s*=\s*(.*)"])',
         hw_name="all",
         drophwnumbelow=0,
         plottype="log",
@@ -417,7 +421,10 @@
         plotfile="l2-write-hits",
         hw_eval='np.average(hw["lts__t_sectors_srcunit_tex_op_write_lookup_hit.sum"])',
         hw_error=None,
-        sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])',
+        sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"])',
         hw_name="all",
         drophwnumbelow=0,
         plottype="log",
@@ -451,8 +458,14 @@
         plotfile="l2-write-hitrate",
         hw_eval='np.average(hw["lts__t_sector_op_write_hit_rate.pct"])',
         hw_error=None,
-        sim_eval='100*float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])/'
-        + 'float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])',
+        sim_eval='100*(float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"]))/'
+        + '(float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[MISS\]\s*=\s*(.*)"])'
+        + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[SECTOR_MISS\]\s*=\s*(.*)"]))',
         hw_name="all",
         drophwnumbelow=0,
         plottype="linear",
diff --git a/util/tracer_nvbit/install_nvbit.sh b/util/tracer_nvbit/install_nvbit.sh
index 0eed71f73b..65af171ac9 100755
--- a/util/tracer_nvbit/install_nvbit.sh
+++ b/util/tracer_nvbit/install_nvbit.sh
@@ -1,8 +1,12 @@
 #!/bin/bash
 export BASH_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )"
 
+# NVBit 1.8 (CUDA 13.2 headers) is required for CUDA-13-era drivers (>=59x).
+# NVBit 1.7.6 supports only driver <=575.xx and produces corrupt register
+# operands on newer drivers (e.g. 596.xx), which crashes post-traces-processing.
+NVBIT_VERSION="1.8"
 rm -rf $BASH_ROOT/nvbit_release
 mkdir -p "$BASH_ROOT/nvbit_release"
-wget https://github.com/NVlabs/NVBit/releases/download/v1.7.6/nvbit-Linux-x86_64-1.7.6.tar.bz2
-tar -xf nvbit-Linux-x86_64-1.7.6.tar.bz2 -C "$BASH_ROOT/nvbit_release" --strip-components=1
-rm nvbit-Linux-x86_64-1.7.6.tar.bz2
+wget https://github.com/NVlabs/NVBit/releases/download/v${NVBIT_VERSION}/nvbit-Linux-x86_64-${NVBIT_VERSION}.tar.bz2
+tar -xf nvbit-Linux-x86_64-${NVBIT_VERSION}.tar.bz2 -C "$BASH_ROOT/nvbit_release" --strip-components=1
+rm nvbit-Linux-x86_64-${NVBIT_VERSION}.tar.bz2