From 0dc90d50ee5bf8c16660df338722cb2ea5d18f82 Mon Sep 17 00:00:00 2001 From: AndrewVu23 Date: Sat, 25 Jul 2026 22:29:01 +0700 Subject: [PATCH 1/2] Add RTX 3060 Laptop support: config, correlation, comparable L2 write-hit, NVBit 1.8 --- .gitignore | 8 ++++++- .../SM86_RTX3060_MOBILE/trace.config | 22 +++++++++++++++++++ .../configs/define-standard-cfgs.yml | 4 ++++ util/job_launching/stats/example_stats.yml | 1 + util/plotting/correl_mappings.py | 21 ++++++++++++++++-- util/tracer_nvbit/install_nvbit.sh | 10 ++++++--- 6 files changed, 60 insertions(+), 6 deletions(-) create mode 100644 gpu-simulator/configs/tested-cfgs/SM86_RTX3060_MOBILE/trace.config diff --git a/.gitignore b/.gitignore index 877bb3f222..73e750178e 100644 --- a/.gitignore +++ b/.gitignore @@ -15,4 +15,10 @@ gpu-simulator/accel_sim.pyi compile_commands.json .cache .cursorrules -CLAUDE.md \ No newline at end of file +.cursor +CLAUDE.md +tutorial +# RTX3060 bring-up working artifacts (not for PR) +util/tuner/stats.txt +util/tuner/gpu-app-collection-partial/ +util/plotting/correl-html/ diff --git a/gpu-simulator/configs/tested-cfgs/SM86_RTX3060_MOBILE/trace.config b/gpu-simulator/configs/tested-cfgs/SM86_RTX3060_MOBILE/trace.config new file mode 100644 index 0000000000..5807e54210 --- /dev/null +++ b/gpu-simulator/configs/tested-cfgs/SM86_RTX3060_MOBILE/trace.config @@ -0,0 +1,22 @@ +-trace_opcode_latency_initiation_int 4,2 +-trace_opcode_latency_initiation_sp 4,2 +-trace_opcode_latency_initiation_dp 64,64 +-trace_opcode_latency_initiation_sfu 23,8 +-trace_opcode_latency_initiation_tensor 32,32 + +#execute branch insts on spec unit 1 +#,,,,, +-specialized_unit_1 1,4,4,4,4,BRA +-trace_opcode_latency_initiation_spec_op_1 4,4 + +#TEX unit, make fixed latency for all tex insts +-specialized_unit_2 1,4,200,4,4,TEX +-trace_opcode_latency_initiation_spec_op_2 200,4 + +#tensor unit +-specialized_unit_3 1,4,32,4,4,TENSOR +-trace_opcode_latency_initiation_spec_op_3 32,32 + +#UDP unit, for turing and above +-specialized_unit_4 1,4,4,4,4,UDP +-trace_opcode_latency_initiation_spec_op_4 4,1 diff --git a/util/job_launching/configs/define-standard-cfgs.yml b/util/job_launching/configs/define-standard-cfgs.yml index 46c0d04b4d..ae453ff835 100644 --- a/util/job_launching/configs/define-standard-cfgs.yml +++ b/util/job_launching/configs/define-standard-cfgs.yml @@ -15,6 +15,10 @@ TITANK: RTX3070: base_file: "$GPGPUSIM_ROOT/configs/tested-cfgs/SM86_RTX3070/gpgpusim.config" +#Ampere RTX 3060 Laptop +RTX3060M: + base_file: "$GPGPUSIM_ROOT/configs/tested-cfgs/SM86_RTX3060_MOBILE/gpgpusim.config" + #Turing RTX2060: base_file: "$GPGPUSIM_ROOT/configs/tested-cfgs/SM75_RTX2060/gpgpusim.config" diff --git a/util/job_launching/stats/example_stats.yml b/util/job_launching/stats/example_stats.yml index ee320e12de..3f9cf12076 100644 --- a/util/job_launching/stats/example_stats.yml +++ b/util/job_launching/stats/example_stats.yml @@ -14,6 +14,7 @@ collect_aggregate: - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_R\]\[HIT\]\s*=\s*(.*)' - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_R\]\[TOTAL_ACCESS\]\s*=\s*(.*)' - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)' + - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)' - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)' - '\s+Total_core_cache_stats_breakdown\[GLOBAL_ACC_R\]\[TOTAL_ACCESS\]\s*=\s*(.*)' - '\s+Total_core_cache_stats_breakdown\[GLOBAL_ACC_R\]\[HIT\]\s*=\s*(.*)' diff --git a/util/plotting/correl_mappings.py b/util/plotting/correl_mappings.py index 671b8bc101..399d660ba8 100644 --- a/util/plotting/correl_mappings.py +++ b/util/plotting/correl_mappings.py @@ -12,6 +12,7 @@ "GV100": set("Quadro GV100"), "RTX2060": set("GeForce RTX 2060"), "RTX3070": set("GeForce RTX 3070"), + "RTX3060M": set(["NVIDIA GeForce RTX 3060 Laptop GPU"]), "A100": set("NVIDIA A100 80GB"), "H100" : set("NVIDIA H100 80GB HBM3"), } @@ -412,12 +413,24 @@ plottype="log", stattype="counter", ), + # NOTE: L2 write-hit comparability is a WORKLOAD property, not a metric defect. + # For read-modify-write workloads (e.g. rodinia hotspot/srad/lud) HW and sim agree + # closely — validated on hotspot: sim HIT=1962 == HW HIT=1962 (~100% both sides). + # It is only meaningless for pure STREAMING-write microbenchmarks, where writes + # target never-read lines: GPGPU-Sim (write-allocate=lazy-fetch-on-read) reports + # ~0% while NVIDIA's sector metric reports ~100% (and can exceed 100%). So keep + # this enabled; just disregard it on streaming-write ubenchs. See + # tutorial/RTX3060_CORRELATION_RESULTS.md "L2 write-hit comparability". CorrelStat( chart_name="L2 Write Hits", plotfile="l2-write-hits", hw_eval='np.average(hw["lts__t_sectors_srcunit_tex_op_write_lookup_hit.sum"])', hw_error=None, - sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])', + # NVIDIA-comparable write hits = strict HIT + WRITE_ALLOCATE (writes absorbed + # into L2 via write-allocate, which NVIDIA counts as hits). WRITE_ALLOCATE is 0 + # for NO_WRITE_ALLOCATE configs, so this reduces to strict HIT there. + sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"])', hw_name="all", drophwnumbelow=0, plottype="log", @@ -446,12 +459,16 @@ plottype="linear", stattype="rate", ), + # See the L2-Write-Hits note above: valid for read-modify-write workloads, + # meaningless only for pure streaming-write microbenchmarks. Kept enabled. CorrelStat( chart_name="L2 Write Hit Rate", plotfile="l2-write-hitrate", hw_eval='np.average(hw["lts__t_sector_op_write_hit_rate.pct"])', hw_error=None, - sim_eval='100*float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])/' + # NVIDIA-comparable rate = 100*(HIT + WRITE_ALLOCATE)/TOTAL_ACCESS. + sim_eval='100*(float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"]))/' + 'float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])', hw_name="all", drophwnumbelow=0, diff --git a/util/tracer_nvbit/install_nvbit.sh b/util/tracer_nvbit/install_nvbit.sh index 0eed71f73b..65af171ac9 100755 --- a/util/tracer_nvbit/install_nvbit.sh +++ b/util/tracer_nvbit/install_nvbit.sh @@ -1,8 +1,12 @@ #!/bin/bash export BASH_ROOT="$( cd "$( dirname "$BASH_SOURCE" )" && pwd )" +# NVBit 1.8 (CUDA 13.2 headers) is required for CUDA-13-era drivers (>=59x). +# NVBit 1.7.6 supports only driver <=575.xx and produces corrupt register +# operands on newer drivers (e.g. 596.xx), which crashes post-traces-processing. +NVBIT_VERSION="1.8" rm -rf $BASH_ROOT/nvbit_release mkdir -p "$BASH_ROOT/nvbit_release" -wget https://github.com/NVlabs/NVBit/releases/download/v1.7.6/nvbit-Linux-x86_64-1.7.6.tar.bz2 -tar -xf nvbit-Linux-x86_64-1.7.6.tar.bz2 -C "$BASH_ROOT/nvbit_release" --strip-components=1 -rm nvbit-Linux-x86_64-1.7.6.tar.bz2 +wget https://github.com/NVlabs/NVBit/releases/download/v${NVBIT_VERSION}/nvbit-Linux-x86_64-${NVBIT_VERSION}.tar.bz2 +tar -xf nvbit-Linux-x86_64-${NVBIT_VERSION}.tar.bz2 -C "$BASH_ROOT/nvbit_release" --strip-components=1 +rm nvbit-Linux-x86_64-${NVBIT_VERSION}.tar.bz2 From 7f8368055e7d4cd6e316fdd605da68eeb8ee0542 Mon Sep 17 00:00:00 2001 From: AndrewVu23 Date: Sun, 26 Jul 2026 14:57:23 +0700 Subject: [PATCH 2/2] Include LOCAL_ACC_W in L2 write correlations (HW counters are all-source) --- util/job_launching/stats/example_stats.yml | 9 ++++++ util/plotting/correl_mappings.py | 32 ++++++++++------------ 2 files changed, 23 insertions(+), 18 deletions(-) diff --git a/util/job_launching/stats/example_stats.yml b/util/job_launching/stats/example_stats.yml index 3f9cf12076..f7821d6633 100644 --- a/util/job_launching/stats/example_stats.yml +++ b/util/job_launching/stats/example_stats.yml @@ -16,6 +16,15 @@ collect_aggregate: - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)' - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)' - '\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)' + # Local-memory writes also traverse L1 -> L2, and NVIDIA's + # lts__t_sectors_srcunit_tex_op_write* counters are all-source, so the L2 write + # correlations must add these. Collected as HIT/MISS/SECTOR_MISS rather than + # TOTAL_ACCESS because GPGPU-Sim only emits a TOTAL_ACCESS line for access types + # with non-zero traffic, whereas these three are always printed (as 0). + - '\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)' + - '\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[MISS\]\s*=\s*(.*)' + - '\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[SECTOR_MISS\]\s*=\s*(.*)' + - '\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)' - '\s+Total_core_cache_stats_breakdown\[GLOBAL_ACC_R\]\[TOTAL_ACCESS\]\s*=\s*(.*)' - '\s+Total_core_cache_stats_breakdown\[GLOBAL_ACC_R\]\[HIT\]\s*=\s*(.*)' - '\s+Total_core_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)' diff --git a/util/plotting/correl_mappings.py b/util/plotting/correl_mappings.py index 399d660ba8..6433150f69 100644 --- a/util/plotting/correl_mappings.py +++ b/util/plotting/correl_mappings.py @@ -407,30 +407,24 @@ plotfile="l2-write-transactions", hw_eval='np.average(hw["lts__t_sectors_srcunit_tex_op_write.sum"])', hw_error=None, - sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])', + sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[MISS\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[SECTOR_MISS\]\s*=\s*(.*)"])', hw_name="all", drophwnumbelow=0, plottype="log", stattype="counter", ), - # NOTE: L2 write-hit comparability is a WORKLOAD property, not a metric defect. - # For read-modify-write workloads (e.g. rodinia hotspot/srad/lud) HW and sim agree - # closely — validated on hotspot: sim HIT=1962 == HW HIT=1962 (~100% both sides). - # It is only meaningless for pure STREAMING-write microbenchmarks, where writes - # target never-read lines: GPGPU-Sim (write-allocate=lazy-fetch-on-read) reports - # ~0% while NVIDIA's sector metric reports ~100% (and can exceed 100%). So keep - # this enabled; just disregard it on streaming-write ubenchs. See - # tutorial/RTX3060_CORRELATION_RESULTS.md "L2 write-hit comparability". CorrelStat( chart_name="L2 Write Hits", plotfile="l2-write-hits", hw_eval='np.average(hw["lts__t_sectors_srcunit_tex_op_write_lookup_hit.sum"])', hw_error=None, - # NVIDIA-comparable write hits = strict HIT + WRITE_ALLOCATE (writes absorbed - # into L2 via write-allocate, which NVIDIA counts as hits). WRITE_ALLOCATE is 0 - # for NO_WRITE_ALLOCATE configs, so this reduces to strict HIT there. sim_eval='float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])' - + ' + float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"])', + + ' + float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"])', hw_name="all", drophwnumbelow=0, plottype="log", @@ -459,17 +453,19 @@ plottype="linear", stattype="rate", ), - # See the L2-Write-Hits note above: valid for read-modify-write workloads, - # meaningless only for pure streaming-write microbenchmarks. Kept enabled. CorrelStat( chart_name="L2 Write Hit Rate", plotfile="l2-write-hitrate", hw_eval='np.average(hw["lts__t_sector_op_write_hit_rate.pct"])', hw_error=None, - # NVIDIA-comparable rate = 100*(HIT + WRITE_ALLOCATE)/TOTAL_ACCESS. sim_eval='100*(float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])' - + ' + float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"]))/' - + 'float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])', + + ' + float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[WRITE_ALLOCATED\]\s*=\s*(.*)"]))/' + + '(float(sim["\s+L2_cache_stats_breakdown\[GLOBAL_ACC_W\]\[TOTAL_ACCESS\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[HIT\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[MISS\]\s*=\s*(.*)"])' + + ' + float(sim["\s+L2_cache_stats_breakdown\[LOCAL_ACC_W\]\[SECTOR_MISS\]\s*=\s*(.*)"]))', hw_name="all", drophwnumbelow=0, plottype="linear",