diff --git a/build_sdk.py b/build_sdk.py
index ebc3adbcb..92cc5bfcb 100644
--- a/build_sdk.py
+++ b/build_sdk.py
@@ -378,6 +378,16 @@ class KernelPath:
             "RPI4_MEMORY": 8192,
         },
     ),
+    BoardInfo(
+        name="rpi5b_2gb",
+        arch=KernelArch.AARCH64,
+        gcc_cpu="cortex-a76",
+        loader_link_address=0x10000000,
+        smp_cores=4,
+        kernel_options={
+            "KernelPlatform": "bcm2712",
+        },
+    ),
     BoardInfo(
         name="rockpro64",
         arch=KernelArch.AARCH64,
diff --git a/docs/manual.md b/docs/manual.md
index 4f757103c..e3d21aa1c 100644
--- a/docs/manual.md
+++ b/docs/manual.md
@@ -1266,6 +1266,7 @@ The currently supported platforms are:
 * rpi4b_2gb
 * rpi4b_4gb
 * rpi4b_8gb
+* rpi5b_2gb
 * serengeti
 * star64
 * stm32mp2
@@ -1530,6 +1531,26 @@ For initial board setup, please see the instructions on the
 When getting into the U-Boot console you want to load the Microkit binary image to
 address 0x10000000 and then run `go 0x10000000`.
 
+For example, if you were to load the image via the MMC you would run the following
+U-Boot commands:
+
+     => fatload mmc 0 0x10000000 <SYSTEM IMAGE>
+     => go 0x10000000
+
+## Raspberry Pi 5B {#rpi5b_2gb}
+
+Support is available for the Raspberry Pi 5 Model B. As of now, the build defaults
+to the 2GB model. This default is set to ensure memory safety across all the memory
+variants of the Pi 5 by limiting the possibility of kernel corruption. If you need
+access to 4GB, 8GB, or 16GB of RAM you will need to supply a custom Device Tree overlay
+via `KernelCustomDTSOverlay` that matches your hardware's memory layout.
+
+For initial board setup, please see the instructions on the
+[seL4 website](https://docs.sel4.systems/Hardware/Rpi5.html).
+
+When getting into the U-Boot console you want to load the Microkit binary image to
+address 0x10000000 and then run `go 0x10000000`.
+
 For example, if you were to load the image via the MMC you would run the following
 U-Boot commands:
 
diff --git a/loader/src/aarch64/cpus.c b/loader/src/aarch64/cpus.c
index b5210751a..9e66ff733 100644
--- a/loader/src/aarch64/cpus.c
+++ b/loader/src/aarch64/cpus.c
@@ -73,6 +73,8 @@ static const size_t psci_target_cpus[4] = {0x00, 0x01, 0x02, 0x03};
 /* BCM2711 does not use PSCI for CPU bring-up. */
 #define SMP_USE_SPIN_TABLE
 static const size_t cpus_release_addr[4] = {0xd8, 0xe0, 0xe8, 0xf0};
+#elif defined(CONFIG_PLAT_BCM2712)
+static const size_t psci_target_cpus[4] = {0x000, 0x100, 0x200, 0x300};
 #else
 
 _Static_assert(!is_set(CONFIG_ENABLE_SMP_SUPPORT),
diff --git a/loader/src/uart.c b/loader/src/uart.c
index 0361da794..890d0b0b5 100644
--- a/loader/src/uart.c
+++ b/loader/src/uart.c
@@ -162,6 +162,27 @@ void putc(uint8_t ch)
     while (!(*UART_REG(MU_LSR) & MU_LSR_TXIDLE));
     *UART_REG(MU_IO) = (ch & 0xff);
 }
+#elif defined(CONFIG_PLAT_BCM2712)
+/* rpi5b */
+#define UART_BASE                 0x107d001000
+#define PL011_TCR                 0x030
+#define PL011_UARTDR              0x000
+#define PL011_UARTFR              0x018
+#define PL011_UARTFR_TXFF         (1 << 5)
+#define PL011_CR_UART_EN          (1 << 0)
+#define PL011_CR_TX_EN            (1 << 8)
+
+void uart_init()
+{
+    /* Enable the device and transmit */
+    *UART_REG(PL011_TCR) |= (PL011_CR_TX_EN | PL011_CR_UART_EN);
+}
+
+void putc(uint8_t ch)
+{
+    while ((*UART_REG(PL011_UARTFR) & PL011_UARTFR_TXFF) != 0);
+    *UART_REG(PL011_UARTDR) = ch;
+}
 #elif defined(CONFIG_PLAT_ROCKPRO64)
 #define UART_BASE   0xff1a0000
 #define UTHR        0x0
diff --git a/platforms.yml b/platforms.yml
index 0588a8110..067caf2d7 100644
--- a/platforms.yml
+++ b/platforms.yml
@@ -14,6 +14,9 @@
 # This list is ordered based on the order in what the platforms were added
 # in.
 platforms:
+  - name: rpi5b_2gb
+    cmake_plat: bcm2712
+    since: dev
   - name: stm32mp2
     cmake_plat: stm32mp2
     since: 2.3.0