From d4c7cf33313a282525ef8670eda1b71e5ff29c0e Mon Sep 17 00:00:00 2001 From: pschatzmann Date: Mon, 6 Jul 2026 10:12:59 +0200 Subject: [PATCH 1/3] ARDUINO_DISCO_F411VE fix broken usb --- variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp b/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp index a5d4688d1f..46e41c100b 100644 --- a/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp +++ b/variants/STM32F4xx/F411V(C-E)T/variant_DISCO_F411VE.cpp @@ -155,7 +155,7 @@ WEAK void SystemClock_Config(void) RCC_OscInitStruct.PLL.PLLM = 4; RCC_OscInitStruct.PLL.PLLN = 192; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; - RCC_OscInitStruct.PLL.PLLQ = 4; + RCC_OscInitStruct.PLL.PLLQ = 8; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { Error_Handler(); } From 72ec2e1b58e219ab4e876ca937fa478f3f08625d Mon Sep 17 00:00:00 2001 From: pschatzmann Date: Mon, 6 Jul 2026 19:54:41 +0200 Subject: [PATCH 2/3] Support for STM32F723E-DISCOVERY --- .gitignore | 1 + README.md | 1 + boards.txt | 15 + .../CMakeLists.txt | 1 + .../variant_DISCO_F723IE.cpp | 289 ++++++++++++++++ .../variant_DISCO_F723IE.h | 313 ++++++++++++++++++ 6 files changed, 620 insertions(+) create mode 100644 variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.cpp create mode 100644 variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.h diff --git a/.gitignore b/.gitignore index 84413bc8ee..bf9af11df1 100644 --- a/.gitignore +++ b/.gitignore @@ -33,3 +33,4 @@ __pycache__/ .vscode/* *.code-workspace .vscode-ctags +.claude/ diff --git a/README.md b/README.md index 80326d2375..b9068a4968 100644 --- a/README.md +++ b/README.md @@ -199,6 +199,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d | :green_heart: | STM32F411VE | [STM32F411E-DISCO](https://www.st.com/en/evaluation-tools/32f411ediscovery.html) | *2.12.0* | | | :green_heart: | STM32F413ZH | [32F413HDISCOVERY](https://www.st.com/en/evaluation-tools/32f413hdiscovery.html) | *1.9.0* | | | :green_heart: | STM32F429I | [STM32F429I-DISC1](https://www.st.com/en/evaluation-tools/32f429idiscovery.html) | *2.12.0* | | +| :yellow_heart: | STM32F723IE | [STM32F723E-DISCOVERY](https://www.st.com/en/evaluation-tools/32f723ediscovery.html) | **3.0.0** | | | :green_heart: | STM32F746NG | [STM32F746G-DISCOVERY](http://www.st.com/en/evaluation-tools/32f746gdiscovery.html) | *0.1.0* | | | :green_heart: | STM32G031J6 | [STM32G0316-DISCO](https://www.st.com/en/evaluation-tools/stm32g0316-disco.html) | *1.9.0* | | | :green_heart: | STM32G431CB | [B-G431B-ESC1](https://www.st.com/en/evaluation-tools/b-g431b-esc1.html) | *2.0.0* | | diff --git a/boards.txt b/boards.txt index b64b8a4910..7749b2d4ec 100644 --- a/boards.txt +++ b/boards.txt @@ -1566,6 +1566,21 @@ Disco.menu.pnum.DISCO_F429ZI.build.variant_h=variant_DISCO_F429ZI.h Disco.menu.pnum.DISCO_F429ZI.openocd.target=stm32f4x Disco.menu.pnum.DISCO_F429ZI.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F4xx/STM32F429.svd +# DISCO_F723IE board +Disco.menu.pnum.DISCO_F723IE=STM32F723E-DISCOVERY +Disco.menu.pnum.DISCO_F723IE.node=DIS_F723IE +Disco.menu.pnum.DISCO_F723IE.upload.maximum_size=524288 +Disco.menu.pnum.DISCO_F723IE.upload.maximum_data_size=196608 +Disco.menu.pnum.DISCO_F723IE.build.mcu=cortex-m7 +Disco.menu.pnum.DISCO_F723IE.build.fpu=-mfpu=fpv5-sp-d16 +Disco.menu.pnum.DISCO_F723IE.build.float-abi=-mfloat-abi=hard +Disco.menu.pnum.DISCO_F723IE.build.board=DISCO_F723IE +Disco.menu.pnum.DISCO_F723IE.build.series=STM32F7xx +Disco.menu.pnum.DISCO_F723IE.build.product_line=STM32F723xx +Disco.menu.pnum.DISCO_F723IE.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) +Disco.menu.pnum.DISCO_F723IE.openocd.target=stm32f7x +Disco.menu.pnum.DISCO_F723IE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F723.svd + # DISCO_F746NG board Disco.menu.pnum.DISCO_F746NG=STM32F746G-DISCOVERY Disco.menu.pnum.DISCO_F746NG.node=DIS_F746NG diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/CMakeLists.txt b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/CMakeLists.txt index 2a4d55b6b1..8eba431eb4 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/CMakeLists.txt +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/CMakeLists.txt @@ -21,6 +21,7 @@ target_link_libraries(variant INTERFACE variant_usage) add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c + variant_DISCO_F723IE.cpp variant_generic.cpp ) target_link_libraries(variant_bin PUBLIC variant_usage) diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.cpp b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.cpp new file mode 100644 index 0000000000..8766b7477b --- /dev/null +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.cpp @@ -0,0 +1,289 @@ +/* + ******************************************************************************* + * Copyright (c) 2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#if defined(ARDUINO_DISCO_F723IE) + +#include "pins_arduino.h" + +// Pin number +const PinName digitalPin[] = { + PA_3, // D0 - USART2_RX + PA_2, // D1 - USART2_TX + PC_5, // D2 + PE_5, // D3 - TIM9_CH1 + PH_3, // D4 + PB_0, // D5 - TIM3_CH3 + PE_6, // D6 - TIM9_CH2 + PE_3, // D7 + PE_4, // D8 + PH_6, // D9 - TIM12_CH1 + PA_1, // D10 - TIM2_CH2 / SPI1_NSS + PB_5, // D11 - TIM3_CH2 / SPI1_MOSI + PB_4, // D12 - SPI1_MISO + PA_5, // D13 - SPI1_SCK + PH_5, // D14 - I2C2_SDA + PH_4, // D15 - I2C2_SCL + PA_6, // A0 + PA_4, // A1 + PC_4, // A2 + PF_10, // A3 - ADC3_IN8 + PC_0, // A4 + PC_1, // A5 + PA_0, // User button + PA_7, // LED_RED + PB_1, // LED_GREEN + PC_6, // ST-LINK VCP TX + PC_7, // ST-LINK VCP RX + PA_8, + PA_9, + PA_10, + PA_11, + PA_12, + PA_13, + PA_14, + PA_15, + PB_2, + PB_3, + PB_6, + PB_7, + PB_8, + PB_9, + PB_10, + PB_11, + PB_12, + PB_13, + PB_14, + PB_15, + PC_2, + PC_3, + PC_8, + PC_9, + PC_10, + PC_11, + PC_12, + PC_13, + PC_14, + PC_15, + PD_0, + PD_1, + PD_2, + PD_3, + PD_4, + PD_5, + PD_6, + PD_7, + PD_8, + PD_9, + PD_10, + PD_11, + PD_12, + PD_13, + PD_14, + PD_15, + PE_0, + PE_1, + PE_2, + PE_7, + PE_8, + PE_9, + PE_10, + PE_11, + PE_12, + PE_13, + PE_14, + PE_15, + PF_0, + PF_1, + PF_2, + PF_3, + PF_4, + PF_5, + PF_6, + PF_7, + PF_8, + PF_9, + PF_11, + PF_12, + PF_13, + PF_14, + PF_15, + PG_0, + PG_1, + PG_2, + PG_3, + PG_4, + PG_5, + PG_8, + PG_9, + PG_10, + PG_11, + PG_12, + PG_13, + PG_14, + PG_15, + PH_0, + PH_1, + PH_2, + PH_7, + PH_8, + PH_9, + PH_10, + PH_11, + PH_12, + PH_13, + PH_14, + PH_15, + PI_0, + PI_1, + PI_2, + PI_3, + PI_4, + PI_5, + PI_6, + PI_7, + PI_8, + PI_9, + PI_10, + PI_11 +}; + +// Analog (Ax) pin number array +const pin_size_t analogInputPin[] = { + 16, // A0 + 17, // A1 + 18, // A2 + 19, // A3 + 20, // A4 + 21 // A5 +}; + +// ---------------------------------------------------------------------------- + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Board-specific early init, called from main() before setup(), + * but after the core has already enabled the Cortex-M7 I/D-Cache + * (see premain() in cores/arduino/main.cpp). + * + * The ARMv7-M *default* memory map treats 0x60000000-0x7FFFFFFF + * (all FMC NOR/SRAM bank windows - PSRAM on NE1 at 0x60000000, the + * on-board LCD on NE2 at 0x64000000) as cacheable "Normal/External + * RAM" unless an MPU region says otherwise. With the D-Cache + * enabled and no MPU region configured, writes to a memory-mapped + * peripheral register interface there (e.g. the LCD's + * command/index and data registers) can get absorbed into the + * cache instead of reaching the external bus: no crash, no hang, + * the external device just never receives a coherent byte stream. + * ST's own reference firmware for this board does the same thing + * for the same reason (see MPU_ConfigPSRAM() in the STM32CubeF7 + * BSP example Applications/Display/LCD_PicturesFromUSB/Src/main.c). + * @param None + * @retval None + */ +WEAK void initVariant(void) +{ + HAL_MPU_Disable(); + + MPU_Region_InitTypeDef mpu = {0}; + mpu.Enable = MPU_REGION_ENABLE; + mpu.BaseAddress = 0x64000000; // FMC Bank2 (NE2, on-board LCD) + mpu.Size = MPU_REGION_SIZE_64MB; // whole NE2 decode window + mpu.AccessPermission = MPU_REGION_FULL_ACCESS; + mpu.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; + mpu.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; + mpu.IsShareable = MPU_ACCESS_SHAREABLE; + mpu.Number = MPU_REGION_NUMBER0; + mpu.TypeExtField = MPU_TEX_LEVEL0; + mpu.SubRegionDisable = 0x00; + mpu.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; + HAL_MPU_ConfigRegion(&mpu); + + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); +} + +/** + * @brief System Clock Configuration + * The system Clock is configured as follows: + * System Clock source = PLL (HSI) + * SYSCLK(Hz) = 216000000 + * HCLK(Hz) = 216000000 + * AHB Prescaler = 1 + * APB1 Prescaler = 4 + * APB2 Prescaler = 2 + * HSI Frequency(Hz) = 16000000 + * PLL_M = 8 + * PLL_N = 216 + * PLL_P = 2 + * PLL_Q = 9 + * VDD(V) = 3.3 + * Main regulator output voltage = Scale1 mode + * Flash Latency(WS) = 7 + * @param None + * @retval None + */ +WEAK void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; + + /* Configure the main internal regulator output voltage */ + __HAL_RCC_PWR_CLK_ENABLE(); + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + + /* Initializes the RCC Oscillators according to the specified parameters */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; + RCC_OscInitStruct.PLL.PLLM = 8; + RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { + Error_Handler(); + } + + /* Activate the Over-Drive mode */ + if (HAL_PWREx_EnableOverDrive() != HAL_OK) { + Error_Handler(); + } + + /* Initializes the CPU, AHB and APB buses clocks */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) { + Error_Handler(); + } + + /* Initializes the peripherals clock (48 MHz for USB OTG FS/HS) */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { + Error_Handler(); + } +} + +#ifdef __cplusplus +} +#endif + +#endif /* ARDUINO_DISCO_F723IE */ diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.h b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.h new file mode 100644 index 0000000000..5d12fa0a74 --- /dev/null +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.h @@ -0,0 +1,313 @@ +/* + ******************************************************************************* + * Copyright (c) 2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#pragma once + +/*---------------------------------------------------------------------------- + * STM32 pins number + *----------------------------------------------------------------------------*/ +// Arduino Uno V3 header +#define PA3 0 // D0 - USART2_RX +#define PA2 1 // D1 - USART2_TX +#define PC5 2 // D2 +#define PE5 3 // D3 - TIM9_CH1 +#define PH3 4 // D4 +#define PB0 5 // D5 - TIM3_CH3 +#define PE6 6 // D6 - TIM9_CH2 +#define PE3 7 // D7 +#define PE4 8 // D8 +#define PH6 9 // D9 - TIM12_CH1 +#define PA1 10 // D10 - TIM2_CH2 / SPI1_NSS +#define PB5 11 // D11 - TIM3_CH2 / SPI1_MOSI +#define PB4 12 // D12 - SPI1_MISO +#define PA5 13 // D13 - SPI1_SCK +#define PH5 14 // D14 - I2C2_SDA +#define PH4 15 // D15 - I2C2_SCL +#define PA6 PIN_A0 +#define PA4 PIN_A1 +#define PC4 PIN_A2 +#define PF10 PIN_A3 // ADC3_IN8 +#define PC0 PIN_A4 +#define PC1 PIN_A5 + +// System / on-board devices +#define PA0 22 // User button (WAKEUP) +#define PA7 23 // LED_RED (LD_USER1) +#define PB1 24 // LED_GREEN (LD_USER2) +#define PC6 25 // ST-LINK VCP TX (USART6_TX) +#define PC7 26 // ST-LINK VCP RX (USART6_RX) + +// Remaining pins (touch panel, USB FS/HS, QSPI flash, FMC LCD/PSRAM bus, +// SAI2 audio codec, PMOD/STMOD+ connectors, WiFi header, ...) +// Not exposed as Dxx/Axx aliases but usable directly through their PinName +// (e.g. digitalWrite(PC9, ...)) by advanced sketches/libraries. +#define PA8 27 // CTP_SCL (I2C3, touch panel) +#define PA9 28 // USB_OTG_FS_VBUS +#define PA10 29 // USB_OTG_FS_ID +#define PA11 30 // USB_OTG_FS_DM +#define PA12 31 // USB_OTG_FS_DP +#define PA13 32 // SWDIO +#define PA14 33 // SWCLK +#define PA15 34 // STMOD TIM2_CH1/ETR +#define PB2 35 // QSPI_CLK +#define PB3 36 // SWO +#define PB6 37 // QSPI_NCS +#define PB7 38 // FMC_NL (NC) +#define PB8 39 // I2C1_SCL (audio codec) +#define PB9 40 // I2C1_SDA (audio codec) +#define PB10 41 // USB_OTG_FS overcurrent +#define PB11 42 // PMOD INT +#define PB12 43 // USB_OTG_HS ID +#define PB13 44 // USB_OTG_HS VBUS +#define PB14 45 // USB_OTG_HS DM +#define PB15 46 // USB_OTG_HS DP +#define PC2 47 // STMOD SPI2 MISO +#define PC3 48 // STMOD SPI2 MOSI +#define PC8 49 // LCD_TE (tearing effect) +#define PC9 50 // QSPI_D0 +#define PC10 51 // QSPI_D1 +#define PC11 52 // STMOD UART4 RX (spare route) +#define PC12 53 // UART5_TX (WiFi header) +#define PC13 54 +#define PC14 55 // OSC32_IN +#define PC15 56 // OSC32_OUT +#define PD0 57 // FMC LCD/PSRAM D2 +#define PD1 58 // FMC LCD/PSRAM D3 +#define PD2 59 // UART5_RX (WiFi header) +#define PD3 60 // WIFI_CH_PD +#define PD4 61 // FMC_NOE +#define PD5 62 // FMC_NWE +#define PD6 63 // WIFI_GPIO2 +#define PD7 64 // FMC_NE1 (PSRAM CS) +#define PD8 65 // FMC LCD/PSRAM D13 +#define PD9 66 // FMC LCD/PSRAM D14 +#define PD10 67 // FMC LCD/PSRAM D15 +#define PD11 68 // FMC_A16/CLE (PSRAM) +#define PD12 69 // FMC_A17/ALE (PSRAM) +#define PD13 70 // QSPI_D3 +#define PD14 71 // FMC LCD/PSRAM D0 +#define PD15 72 // FMC LCD/PSRAM D1 +#define PE0 73 // FMC_NBL0 (PSRAM) +#define PE1 74 // FMC_NBL1 (PSRAM) +#define PE2 75 // QSPI_D2 +#define PE7 76 // FMC LCD/PSRAM D4 +#define PE8 77 // FMC LCD/PSRAM D5 +#define PE9 78 // FMC LCD/PSRAM D6 +#define PE10 79 // FMC LCD/PSRAM D7 +#define PE11 80 // FMC LCD/PSRAM D8 +#define PE12 81 // FMC LCD/PSRAM D9 +#define PE13 82 // FMC LCD/PSRAM D10 +#define PE14 83 // FMC LCD/PSRAM D11 +#define PE15 84 // FMC LCD/PSRAM D12 +#define PF0 85 // FMC_A0 (PSRAM) +#define PF1 86 // FMC_A1 (PSRAM) +#define PF2 87 // FMC_A2 (PSRAM) +#define PF3 88 // FMC_A3 (PSRAM) +#define PF4 89 // FMC_A4 (PSRAM) +#define PF5 90 // FMC_A5 (PSRAM) +#define PF6 91 // PMOD UART7 RX +#define PF7 92 // PMOD UART7 TX +#define PF8 93 // PMOD UART7 RTS +#define PF9 94 // PMOD UART7 CTS +#define PF11 95 // PMOD RESET +#define PF12 96 // FMC_A6 (PSRAM) +#define PF13 97 // FMC_A7 (PSRAM) +#define PF14 98 // FMC_A8 (PSRAM) +#define PF15 99 // FMC_A9 (PSRAM) +#define PG0 100 // FMC_A10 (PSRAM) +#define PG1 101 // FMC_A11 (PSRAM) +#define PG2 102 // FMC_A12 (PSRAM) +#define PG3 103 // FMC_A13 (PSRAM) +#define PG4 104 // FMC_A14/BA0 (PSRAM) +#define PG5 105 // FMC_A15/BA1 (PSRAM) +#define PG8 106 // USB_OTG_FS power switch enable +#define PG9 107 // FMC_NE2 (LCD CS) +#define PG10 108 // SAI2_SD_B (audio codec) +#define PG11 109 +#define PG12 110 // PMOD GPIO0 +#define PG13 111 // WIFI_GPIO0 +#define PG14 112 // WIFI_RST +#define PG15 113 // SAI2_INT (audio codec IRQ) +#define PH0 114 // OSC_IN (HSE) +#define PH1 115 // OSC_OUT (HSE) +#define PH2 116 // PMOD GPIO1 +#define PH7 117 // LCD_RST +#define PH8 118 // CTP_SDA +#define PH9 119 // CTP_RST +#define PH10 120 // USB_OTG_HS overcurrent +#define PH11 121 // LCD_BL (backlight enable) +#define PH12 122 // USB_OTG_HS power switch enable +#define PH13 123 // STMOD UART4 TX +#define PH14 124 // STMOD UART4 RX +#define PH15 125 // PMOD SEL0 +#define PI0 126 // PMOD SPI2 NSS +#define PI1 127 // PMOD SPI2 SCK +#define PI2 128 // PMOD SPI2 MISO +#define PI3 129 // PMOD SPI2 MOSI +#define PI4 130 // SAI2_MCLK_A (audio codec) +#define PI5 131 // SAI2_SCK_A (audio codec) +#define PI6 132 // SAI2_SD_A (audio codec) +#define PI7 133 // SAI2_FS_A (audio codec) +#define PI8 134 +#define PI9 135 // CTP_INT +#define PI10 136 +#define PI11 137 + +// Alternate pins number +#define PA0_ALT1 (PA0 | ALT1) +#define PA0_ALT2 (PA0 | ALT2) +#define PA1_ALT1 (PA1 | ALT1) +#define PA1_ALT2 (PA1 | ALT2) +#define PA2_ALT1 (PA2 | ALT1) +#define PA2_ALT2 (PA2 | ALT2) +#define PA3_ALT1 (PA3 | ALT1) +#define PA3_ALT2 (PA3 | ALT2) +#define PA4_ALT1 (PA4 | ALT1) +#define PA5_ALT1 (PA5 | ALT1) +#define PA6_ALT1 (PA6 | ALT1) +#define PA7_ALT1 (PA7 | ALT1) +#define PA7_ALT2 (PA7 | ALT2) +#define PA7_ALT3 (PA7 | ALT3) +#define PA15_ALT1 (PA15 | ALT1) +#define PB0_ALT1 (PB0 | ALT1) +#define PB0_ALT2 (PB0 | ALT2) +#define PB1_ALT1 (PB1 | ALT1) +#define PB1_ALT2 (PB1 | ALT2) +#define PB3_ALT1 (PB3 | ALT1) +#define PB4_ALT1 (PB4 | ALT1) +#define PB5_ALT1 (PB5 | ALT1) +#define PB8_ALT1 (PB8 | ALT1) +#define PB9_ALT1 (PB9 | ALT1) +#define PC0_ALT1 (PC0 | ALT1) +#define PC0_ALT2 (PC0 | ALT2) +#define PC1_ALT1 (PC1 | ALT1) +#define PC1_ALT2 (PC1 | ALT2) +#define PC2_ALT1 (PC2 | ALT1) +#define PC2_ALT2 (PC2 | ALT2) +#define PC3_ALT1 (PC3 | ALT1) +#define PC3_ALT2 (PC3 | ALT2) +#define PC4_ALT1 (PC4 | ALT1) +#define PC5_ALT1 (PC5 | ALT1) +#define PC6_ALT1 (PC6 | ALT1) +#define PC7_ALT1 (PC7 | ALT1) +#define PC8_ALT1 (PC8 | ALT1) +#define PC9_ALT1 (PC9 | ALT1) +#define PC10_ALT1 (PC10 | ALT1) +#define PC11_ALT1 (PC11 | ALT1) + +#define NUM_DIGITAL_PINS 138 +#define NUM_ANALOG_INPUTS 6 + +// On-board LED pin number +#ifndef LED_BUILTIN + #define LED_BUILTIN PA7 +#endif +#define LED_RED PA7 +#define LED_GREEN PB1 + +// On-board user button +#ifndef USER_BTN + #define USER_BTN PA0 +#endif + +// SPI definitions (Arduino Uno V3 header, SPI1) +#ifndef PIN_SPI_SS + #define PIN_SPI_SS PA1 +#endif +#ifndef PIN_SPI_MOSI + #define PIN_SPI_MOSI PB5 +#endif +#ifndef PIN_SPI_MISO + #define PIN_SPI_MISO PB4 +#endif +#ifndef PIN_SPI_SCK + #define PIN_SPI_SCK PA5 +#endif + +// I2C definitions (Arduino Uno V3 header, I2C2) +#ifndef PIN_WIRE_SDA + #define PIN_WIRE_SDA PH5 +#endif +#ifndef PIN_WIRE_SCL + #define PIN_WIRE_SCL PH4 +#endif + +// Timer Definitions +// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin +#ifndef TIMER_TONE + #define TIMER_TONE TIM6 +#endif +#ifndef TIMER_SERVO + #define TIMER_SERVO TIM7 +#endif + +// UART Definitions +#ifndef SERIAL_UART_INSTANCE + #define SERIAL_UART_INSTANCE 6 // Connected to ST-Link VCP (USART6) +#endif + +// Default pin used for 'Serial' instance (ex: ST-Link) +// Mandatory for Firmata +#ifndef PIN_SERIAL_RX + #define PIN_SERIAL_RX PC7 +#endif +#ifndef PIN_SERIAL_TX + #define PIN_SERIAL_TX PC6 +#endif + +// SDMMC signals not available +#define SDMMC_CKIN_NA +#define SDMMC_CDIR_NA +#define SDMMC_D0DIR_NA +#define SDMMC_D123DIR_NA + +// Extra HAL modules +#if !defined(HAL_DAC_MODULE_DISABLED) + #define HAL_DAC_MODULE_ENABLED +#endif +#if !defined(HAL_QSPI_MODULE_DISABLED) + #define HAL_QSPI_MODULE_ENABLED +#endif +#if !defined(HAL_SRAM_MODULE_DISABLED) + #define HAL_SRAM_MODULE_ENABLED +#endif +#if !defined(HAL_SAI_MODULE_DISABLED) + #define HAL_SAI_MODULE_ENABLED +#endif + +/*---------------------------------------------------------------------------- + * Arduino objects - C++ only + *----------------------------------------------------------------------------*/ + +#ifdef __cplusplus + // These serial port names are intended to allow libraries and architecture-neutral + // sketches to automatically default to the correct port name for a particular type + // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN, + // the first hardware serial port whose RX/TX pins are not dedicated to another use. + // + // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor + // + // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial + // + // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library + // + // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins. + // + // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX + // pins are NOT connected to anything by default. + #ifndef SERIAL_PORT_MONITOR + #define SERIAL_PORT_MONITOR Serial + #endif + #ifndef SERIAL_PORT_HARDWARE + #define SERIAL_PORT_HARDWARE Serial + #endif +#endif From 97d186ee8c7924fa4a682cf98ae9719bb83e94ad Mon Sep 17 00:00:00 2001 From: pschatzmann Date: Tue, 7 Jul 2026 17:55:08 +0200 Subject: [PATCH 3/3] Using HSE & custom peripheral pins --- boards.txt | 1 + .../CMakeLists.txt | 1 + .../PeripheralPins_DISCO_F723IE.c | 614 ++++++++++++++++++ .../variant_DISCO_F723IE.cpp | 19 +- 4 files changed, 625 insertions(+), 10 deletions(-) create mode 100644 variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins_DISCO_F723IE.c diff --git a/boards.txt b/boards.txt index 7749b2d4ec..10b91f71bd 100644 --- a/boards.txt +++ b/boards.txt @@ -1578,6 +1578,7 @@ Disco.menu.pnum.DISCO_F723IE.build.board=DISCO_F723IE Disco.menu.pnum.DISCO_F723IE.build.series=STM32F7xx Disco.menu.pnum.DISCO_F723IE.build.product_line=STM32F723xx Disco.menu.pnum.DISCO_F723IE.build.variant=STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T) +Disco.menu.pnum.DISCO_F723IE.build.peripheral_pins=-DCUSTOM_PERIPHERAL_PINS Disco.menu.pnum.DISCO_F723IE.openocd.target=stm32f7x Disco.menu.pnum.DISCO_F723IE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32F7xx/STM32F723.svd diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/CMakeLists.txt b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/CMakeLists.txt index 8eba431eb4..4353056c3c 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/CMakeLists.txt +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/CMakeLists.txt @@ -21,6 +21,7 @@ target_link_libraries(variant INTERFACE variant_usage) add_library(variant_bin STATIC EXCLUDE_FROM_ALL generic_clock.c PeripheralPins.c + PeripheralPins_DISCO_F723IE.c variant_DISCO_F723IE.cpp variant_generic.cpp ) diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins_DISCO_F723IE.c b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins_DISCO_F723IE.c new file mode 100644 index 0000000000..a4b0a25b43 --- /dev/null +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/PeripheralPins_DISCO_F723IE.c @@ -0,0 +1,614 @@ +/* + ******************************************************************************* + * Copyright (c) 2026, STMicroelectronics + * All rights reserved. + * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +/* + * Automatically generated from STM32F723I(C-E)Kx.xml, STM32F723I(C-E)Tx.xml + * STM32F730I8Kx.xml, STM32F733IEKx.xml + * STM32F733IETx.xml + * CubeMX DB release 6.0.180 + * + * Board-specific edits for STM32F723E-DISCOVERY (see comments below). + */ +#if defined(ARDUINO_DISCO_F723IE) +#include "Arduino.h" +#include "PeripheralPins.h" + +/* ===== + * Notes: + * - The pins mentioned Px_y_ALTz are alternative possibilities which use other + * HW peripheral instances. You can use them the same way as any other "normal" + * pin (i.e. analogWrite(PA7_ALT1, 128);). + * + * - Commented lines are alternative possibilities which are not used per default. + * If you change them, you will have to know what you do + * + * - On this board, some pins are hardwired to on-board, permanently-populated + * devices: the QSPI NOR flash, the FMC-driven LCD panel + PSRAM (sharing one + * 16-bit data/address bus), the WM8994 audio codec (I2C1 + SAI2), the + * capacitive touch controller (I2C3), the ST-LINK Virtual COM Port + * (USART6/PC6-PC7), and the USB FS/HS connectors. Their alternate-function + * entries for *other* peripherals are commented out below so a stray + * analogRead()/analogWrite()/Wire()/SPI()/Serial()/CAN call on those pins + * can't silently reconfigure a pin that's actively driving one of those + * fixed devices. Pins that only go to optional/removable connectors + * (Arduino Uno header, PMOD, STMOD+, the WiFi add-on header) are left as-is, + * since any conflict there is under the user's own control. + * + * Exception: PH_11 (LCD_BL, the backlight-enable line) keeps its TIM5_CH2 + * entry, since PWM-driving it for brightness control is a legitimate, + * commonly desired use rather than a conflict. + * + * - This board has no on-board SD/microSD slot, so the whole SD/SDMMC1 pin + * map is disabled below: its 8-bit-wide pin set otherwise overlaps the + * QSPI flash, the LCD tearing-effect input, the WiFi header UART, the + * audio codec I2C, and the ST-LINK VCP UART. + * + * - This board has no ULPI PHY populated, so USB_OTG_HS only ever runs in + * internal-FS-PHY mode; the ULPI pin set is disabled below. + * ===== + */ + +//*** ADC *** + +#ifdef HAL_ADC_MODULE_ENABLED +WEAK const PinMap PinMap_ADC[] = { + {PA_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC1_IN0 + {PA_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC2_IN0 + {PA_0_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 0, 0)}, // ADC3_IN0 + {PA_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC1_IN1 + {PA_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC2_IN1 + {PA_1_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // ADC3_IN1 + {PA_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC1_IN2 + {PA_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC2_IN2 + {PA_2_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // ADC3_IN2 + {PA_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC1_IN3 + {PA_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC2_IN3 + {PA_3_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 3, 0)}, // ADC3_IN3 + {PA_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC1_IN4 + {PA_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC2_IN4 + {PA_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC1_IN5 + {PA_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC2_IN5 + {PA_6, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC1_IN6 + {PA_6_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC2_IN6 + {PA_7, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC1_IN7 + {PA_7_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC2_IN7 + {PB_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC1_IN8 + {PB_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC2_IN8 + {PB_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC1_IN9 + {PB_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC2_IN9 + {PC_0, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC1_IN10 + {PC_0_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC2_IN10 + {PC_0_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 10, 0)}, // ADC3_IN10 + {PC_1, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC1_IN11 + {PC_1_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC2_IN11 + {PC_1_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 11, 0)}, // ADC3_IN11 + {PC_2, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC1_IN12 + {PC_2_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC2_IN12 + {PC_2_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 12, 0)}, // ADC3_IN12 + {PC_3, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC1_IN13 + {PC_3_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC2_IN13 + {PC_3_ALT2, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 13, 0)}, // ADC3_IN13 + {PC_4, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC1_IN14 + {PC_4_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC2_IN14 + {PC_5, ADC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC1_IN15 + {PC_5_ALT1, ADC2, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC2_IN15 + // {PF_3, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 9, 0)}, // ADC3_IN9 -- PSRAM_A3 + // {PF_4, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 14, 0)}, // ADC3_IN14 -- PSRAM_A4 + // {PF_5, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 15, 0)}, // ADC3_IN15 -- PSRAM_A5 + {PF_6, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 4, 0)}, // ADC3_IN4 + {PF_7, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 5, 0)}, // ADC3_IN5 + {PF_8, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 6, 0)}, // ADC3_IN6 + {PF_9, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 7, 0)}, // ADC3_IN7 + {PF_10, ADC3, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 8, 0)}, // ADC3_IN8 + {NC, NP, 0} +}; +#endif + +//*** DAC *** + +#ifdef HAL_DAC_MODULE_ENABLED +WEAK const PinMap PinMap_DAC[] = { + {PA_4, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 1, 0)}, // DAC_OUT1 + {PA_5, DAC1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, LL_GPIO_PULL_NO, 0, 2, 0)}, // DAC_OUT2 + {NC, NP, 0} +}; +#endif + +//*** I2C *** + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SDA[] = { + {PB_7, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, + {PB_9, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, // audio codec SDA + {PB_11, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, + // {PC_9, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, -- QUADSPI_D0 + // {PF_0, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, -- PSRAM_A0 + {PH_5, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, // Arduino header D14 (PIN_WIRE_SDA) + {PH_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, // touch controller SDA + {NC, NP, 0} +}; +#endif + +#ifdef HAL_I2C_MODULE_ENABLED +WEAK const PinMap PinMap_I2C_SCL[] = { + {PA_8, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, // touch controller SCL + // {PB_6, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, -- QUADSPI_NCS + {PB_8, I2C1, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C1)}, // audio codec SCL + // {PB_10, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, -- USB_OTG_FS overcurrent + // {PF_1, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, -- PSRAM_A1 + {PH_4, I2C2, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C2)}, // Arduino header D15 (PIN_WIRE_SCL) + // {PH_7, I2C3, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_NO, GPIO_AF4_I2C3)}, -- LCD_RST + {NC, NP, 0} +}; +#endif + +//*** No I3C *** + +//*** TIM *** + +#ifdef HAL_TIM_MODULE_ENABLED +WEAK const PinMap PinMap_TIM[] = { + {PA_0, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_0_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 + {PA_1, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PA_1_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 + {PA_2, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 + {PA_2_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 + {PA_2_ALT2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PA_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + {PA_3_ALT1, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PA_3_ALT2, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + {PA_5, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PA_5_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PA_6_ALT1, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PA_7, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N + {PA_7_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + {PA_7_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PA_7_ALT3, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + // {PA_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 -- touch I2C3_SCL + // {PA_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 -- USB_OTG_FS_VBUS + // {PA_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 -- USB_OTG_FS_ID + // {PA_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 -- USB_OTG_FS_DM + {PA_15, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 + {PB_0, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N + {PB_0_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 + {PB_0_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PB_1, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N + {PB_1_ALT1, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 + {PB_1_ALT2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PB_3, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 + {PB_4, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 + {PB_5, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 + // {PB_6, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 -- QUADSPI_NCS + {PB_7, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 + // {PB_8, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -- audio I2C1_SCL + // {PB_8_ALT1, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 -- audio I2C1_SCL + // {PB_9, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 -- audio I2C1_SDA + // {PB_9_ALT1, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 -- audio I2C1_SDA + // {PB_10, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 -- USB_OTG_FS overcurrent + {PB_11, TIM2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 + // {PB_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N -- USB_OTG_HS_VBUS + // {PC_6, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1 -- ST-LINK VCP TX + // {PC_6_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 -- ST-LINK VCP TX + // {PC_7, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2 -- ST-LINK VCP RX + // {PC_7_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 -- ST-LINK VCP RX + // {PC_8, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3 -- LCD_TE + // {PC_8_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 -- LCD_TE + // {PC_9, TIM3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4 -- QUADSPI_D0 + // {PC_9_ALT1, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 -- QUADSPI_D0 + // {PD_12, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1 -- PSRAM_A17 + // {PD_13, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2 -- QUADSPI_D3 + // {PD_14, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3 -- LCD/PSRAM D0 + // {PD_15, TIM4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4 -- LCD/PSRAM D1 + {PE_5, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1 + {PE_6, TIM9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2 + // {PE_8, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N -- LCD/PSRAM D5 + // {PE_9, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1 -- LCD/PSRAM D6 + // {PE_10, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N -- LCD/PSRAM D7 + // {PE_11, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2 -- LCD/PSRAM D8 + // {PE_12, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N -- LCD/PSRAM D9 + // {PE_13, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3 -- LCD/PSRAM D10 + // {PE_14, TIM1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4 -- LCD/PSRAM D11 + {PF_6, TIM10, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1 + {PF_7, TIM11, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1 + {PF_8, TIM13, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM13, 1, 0)}, // TIM13_CH1 + {PF_9, TIM14, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM14, 1, 0)}, // TIM14_CH1 + {PH_6, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM12, 1, 0)}, // TIM12_CH1 + // {PH_9, TIM12, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_TIM12, 2, 0)}, // TIM12_CH2 -- touch CTP_RST + // {PH_10, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 -- USB_OTG_HS overcurrent + {PH_11, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 -- LCD_BL (PWM backlight dimming, kept on purpose) + // {PH_12, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 -- USB_OTG_HS power switch enable + {PH_13, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 1)}, // TIM8_CH1N + {PH_14, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 1)}, // TIM8_CH2N + {PH_15, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 1)}, // TIM8_CH3N + {PI_0, TIM5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 + {PI_2, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 4, 0)}, // TIM8_CH4 + // {PI_5, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 1, 0)}, // TIM8_CH1 -- audio SAI2_SCK_A + // {PI_6, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 2, 0)}, // TIM8_CH2 -- audio SAI2_SD_A + // {PI_7, TIM8, STM_PIN_DATA_EXT(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF3_TIM8, 3, 0)}, // TIM8_CH3 -- audio SAI2_FS_A + {NC, NP, 0} +}; +#endif + +//*** UART *** + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_TX[] = { + {PA_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_2, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, // Arduino header D1 + // {PA_9, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, -- USB_OTG_FS_VBUS + // {PB_6, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, -- QUADSPI_NCS + // {PB_10, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, -- USB_OTG_FS overcurrent + {PC_6, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_USART6)}, // ST-LINK VCP TX + // {PC_10, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, -- QUADSPI_D1 + // {PC_10_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, -- QUADSPI_D1 + {PC_12, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, // WiFi header TX + // {PD_5, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, -- FMC_NWE + // {PD_8, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, -- LCD/PSRAM D13 + // {PE_1, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, -- PSRAM_NBL1 + // {PE_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART7)}, -- LCD/PSRAM D5 + {PF_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART7)}, // PMOD UART7 TX + {PG_14, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_USART6)}, + {PH_13, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, // STMOD UART4 TX + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RX[] = { + {PA_1, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PA_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, // Arduino header D0 + // {PA_10, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, -- USB_OTG_FS_ID + {PB_7, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, + {PB_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PC_7, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_USART6)}, // ST-LINK VCP RX + {PC_11, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + {PC_11_ALT1, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, + {PD_2, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART5)}, // WiFi header RX + {PD_6, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + // {PD_9, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, -- LCD/PSRAM D14 + // {PE_0, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, -- PSRAM_NBL0 + // {PE_7, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART7)}, -- LCD/PSRAM D4 + {PF_6, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART7)}, // PMOD UART7 RX + // {PG_9, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_USART6)}, -- LCD_NE (FMC_NE2) + {PH_14, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, // STMOD UART4 RX + // {PI_9, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, -- touch CTP_INT + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_RTS[] = { + {PA_1, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + // {PA_12, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, -- USB_OTG_FS_DP + {PA_15, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + // {PC_8, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART5)}, -- LCD_TE + // {PD_4, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, -- FMC_NOE + // {PD_12, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, -- PSRAM_A17 + // {PD_15, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, -- LCD/PSRAM D1 + // {PE_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART7)}, -- LCD/PSRAM D6 + {PF_8, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART7)}, // PMOD UART7 RTS + // {PG_8, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_USART6)}, -- USB_OTG_FS power switch enable + {PG_12, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_USART6)}, + {NC, NP, 0} +}; +#endif + +#ifdef HAL_UART_MODULE_ENABLED +WEAK const PinMap PinMap_UART_CTS[] = { + {PA_0, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + // {PA_11, USART1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART1)}, -- USB_OTG_FS_DM + {PB_0, UART4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART4)}, + // {PB_13, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, -- USB_OTG_HS_VBUS + // {PC_9, UART5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_UART5)}, -- QUADSPI_D0 + {PD_3, USART2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART2)}, + // {PD_11, USART3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_USART3)}, -- PSRAM_A16 + // {PD_14, UART8, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART8)}, -- LCD/PSRAM D0 + // {PE_10, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART7)}, -- LCD/PSRAM D7 + {PF_9, UART7, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_UART7)}, // PMOD UART7 CTS + {PG_13, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_USART6)}, + // {PG_15, USART6, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF8_USART6)}, -- audio SAI2_INT + {NC, NP, 0} +}; +#endif + +//*** SPI *** + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MOSI[] = { + {PA_7, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + // {PB_2, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI3)}, -- QUADSPI_CLK + {PB_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, // Arduino header D11 (PIN_SPI_MOSI) + {PB_5_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PC_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + {PC_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, // STMOD SPI2 MOSI + {PC_12, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PD_6, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI3)}, + {PE_6, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + // {PE_14, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, -- LCD/PSRAM D11 + {PF_9, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)}, + {PF_11, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)}, + {PI_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, // PMOD SPI2 MOSI + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_MISO[] = { + {PA_6, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, // Arduino header D12 (PIN_SPI_MISO) + {PB_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PC_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, // STMOD SPI2 MISO + {PC_11, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PE_5, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + // {PE_13, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, -- LCD/PSRAM D10 + {PF_8, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)}, + // {PH_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)}, -- LCD_RST + {PI_2, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, // PMOD SPI2 MISO + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SCLK[] = { + {PA_5, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, // Arduino header D13 (PIN_SPI_SCK) + // {PA_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, -- USB_OTG_FS_VBUS + {PB_3, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PB_3_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + // {PB_10, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, -- USB_OTG_FS overcurrent + // {PB_13, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, -- USB_OTG_HS_VBUS + // {PC_10, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, -- QUADSPI_D1 + {PD_3, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, + // {PE_2, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, -- QUADSPI_D2 + // {PE_12, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, -- LCD/PSRAM D9 + {PF_7, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)}, + {PH_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)}, + {PI_1, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, // PMOD SPI2 SCK + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SPI_MODULE_ENABLED +WEAK const PinMap PinMap_SPI_SSEL[] = { + {PA_4, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_4_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PA_15, SPI1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI1)}, + {PA_15_ALT1, SPI3, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF6_SPI3)}, + {PB_4, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF7_SPI2)}, + // {PB_9, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, -- audio I2C1_SDA + // {PB_12, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, -- USB_OTG_HS_ID + {PE_4, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, + // {PE_11, SPI4, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI4)}, -- LCD/PSRAM D8 + {PF_6, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)}, + {PH_5, SPI5, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI5)}, + {PI_0, SPI2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF5_SPI2)}, // PMOD SPI2 NSS + {NC, NP, 0} +}; +#endif + +//*** CAN *** + +#if defined(HAL_CAN_MODULE_ENABLED) || defined(HAL_CAN_LEGACY_MODULE_ENABLED) +WEAK const PinMap PinMap_CAN_RD[] = { + // {PA_11, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, -- USB_OTG_FS_DM + // {PB_8, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, -- audio I2C1_SCL + // {PD_0, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, -- LCD/PSRAM D2 + {PH_14, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, // STMOD UART4 RX + // {PI_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, -- touch CTP_INT + {NC, NP, 0} +}; +#endif + +#if defined(HAL_CAN_MODULE_ENABLED) || defined(HAL_CAN_LEGACY_MODULE_ENABLED) +WEAK const PinMap PinMap_CAN_TD[] = { + // {PA_12, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, -- USB_OTG_FS_DP + // {PB_9, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, -- audio I2C1_SDA + // {PD_1, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, -- LCD/PSRAM D3 + {PH_13, CAN1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF9_CAN1)}, // STMOD UART4 TX + {NC, NP, 0} +}; +#endif + +//*** No ETHERNET *** + +//*** QUADSPI *** + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA0[] = { + {PC_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 (on-board flash) + // {PD_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO0 -- PSRAM_A16 + // {PE_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO0 -- LCD/PSRAM D4 + {PF_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO0 + {PH_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO0 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA1[] = { + {PC_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 (on-board flash) + // {PD_12, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO1 -- PSRAM_A17 + // {PE_8, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO1 -- LCD/PSRAM D5 + {PF_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_IO1 + {PH_3, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA2[] = { + {PE_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 (on-board flash) + // {PE_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO2 -- LCD/PSRAM D6 + {PF_7, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO2 + // {PG_9, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO2 -- LCD_NE (FMC_NE2) + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_DATA3[] = { + {PA_1, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PD_13, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 (on-board flash) + // {PE_10, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK2_IO3 -- LCD/PSRAM D7 + {PF_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK1_IO3 + {PG_14, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_IO3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_SCLK[] = { + {PB_2, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_CLK (on-board flash) + {NC, NP, 0} +}; +#endif + +#ifdef HAL_QSPI_MODULE_ENABLED +WEAK const PinMap PinMap_QUADSPI_SSEL[] = { + {PB_6, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_QUADSPI)}, // QUADSPI_BK1_NCS (on-board flash) + {PC_11, QUADSPI, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF9_QUADSPI)}, // QUADSPI_BK2_NCS + {NC, NP, 0} +}; +#endif + +//*** USB *** + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_FS[] = { + // {PA_8, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_SOF -- touch I2C3_SCL + {PA_9, USB_OTG_FS, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_OTG_FS_VBUS + {PA_10, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_ID + {PA_11, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DM + {PA_12, USB_OTG_FS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_FS)}, // USB_OTG_FS_DP + {NC, NP, 0} +}; +#endif + +#if defined(HAL_PCD_MODULE_ENABLED) || defined(HAL_HCD_MODULE_ENABLED) +WEAK const PinMap PinMap_USB_OTG_HS[] = { +#ifdef USE_USB_HS_IN_FS + {PA_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_SOF + {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_OD, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_ID + {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_INPUT, LL_GPIO_PULL_NO, GPIO_AF_NONE)}, // USB_OTG_HS_VBUS + {PB_14, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DM + {PB_15, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_OTG_HS_FS)}, // USB_OTG_HS_DP +#else + // No ULPI PHY is populated on this board: USB_OTG_HS only ever runs in + // internal-FS-PHY mode (see the USE_USB_HS_IN_FS branch above). + // {PA_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D0 + // {PA_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_CK + // {PB_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D1 + // {PB_1, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D2 + // {PB_5, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D7 + // {PB_10, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D3 + // {PB_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D4 + // {PB_12, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D5 + // {PB_13, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_D6 + // {PC_0, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_STP + // {PC_2, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR + // {PC_3, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT + // {PH_4, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_NXT + // {PI_11, USB_OTG_HS, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_OTG_HS)}, // USB_OTG_HS_ULPI_DIR +#endif /* USE_USB_HS_IN_FS */ + {NC, NP, 0} +}; +#endif + +//*** SD *** +// No microSD/SD slot on this board: the SDMMC1 pin set is disabled below +// since it would otherwise overlap the QSPI flash, the LCD tearing-effect +// input, the WiFi header UART, the audio codec I2C, and the ST-LINK VCP UART. + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CMD[] = { + // {PD_2, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CMD -- WiFi header RX + // {PD_7, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC2)}, // SDMMC2_CMD -- PSRAM_NE1 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_CK[] = { + // {PC_12, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF12_SDMMC1)}, // SDMMC1_CK -- WiFi header TX + // {PD_6, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_NO, GPIO_AF11_SDMMC2)}, // SDMMC2_CK -- WiFi header GPIO2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA0[] = { + // {PC_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D0 -- LCD_TE + // {PG_9, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC2)}, // SDMMC2_D0 -- LCD_NE (FMC_NE2) + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA1[] = { + // {PC_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D1 -- QUADSPI_D0 + // {PG_10, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC2)}, // SDMMC2_D1 -- audio SAI2_SD_B + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA2[] = { + // {PB_3, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 + // {PC_10, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D2 -- QUADSPI_D1 + // {PG_11, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D2 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA3[] = { + // {PB_4, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D3 -- Arduino header D12 + // {PC_11, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D3 + // {PG_12, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF11_SDMMC2)}, // SDMMC2_D3 + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA4[] = { + // {PB_8, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D4 -- audio I2C1_SCL + // {PB_8_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D4 -- audio I2C1_SCL + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA5[] = { + // {PB_9, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D5 -- audio I2C1_SDA + // {PB_9_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D5 -- audio I2C1_SDA + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA6[] = { + // {PC_6, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D6 -- ST-LINK VCP TX + // {PC_6_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D6 -- ST-LINK VCP TX + {NC, NP, 0} +}; +#endif + +#ifdef HAL_SD_MODULE_ENABLED +WEAK const PinMap PinMap_SD_DATA7[] = { + // {PC_7, SDMMC1, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF12_SDMMC1)}, // SDMMC1_D7 -- ST-LINK VCP RX + // {PC_7_ALT1, SDMMC2, STM_PIN_DATA(STM_MODE_AF_PP, LL_GPIO_PULL_UP, GPIO_AF10_SDMMC2)}, // SDMMC2_D7 -- ST-LINK VCP RX + {NC, NP, 0} +}; +#endif + +#endif /* ARDUINO_DISCO_F723IE */ diff --git a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.cpp b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.cpp index 8766b7477b..bfb7ce2c76 100644 --- a/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.cpp +++ b/variants/STM32F7xx/F723I(C-E)(K-T)_F730I8K_F733IE(K-T)/variant_DISCO_F723IE.cpp @@ -216,15 +216,15 @@ WEAK void initVariant(void) /** * @brief System Clock Configuration * The system Clock is configured as follows: - * System Clock source = PLL (HSI) + * System Clock source = PLL (HSE) * SYSCLK(Hz) = 216000000 * HCLK(Hz) = 216000000 * AHB Prescaler = 1 * APB1 Prescaler = 4 * APB2 Prescaler = 2 - * HSI Frequency(Hz) = 16000000 - * PLL_M = 8 - * PLL_N = 216 + * HSE Frequency(Hz) = 25000000 + * PLL_M = 25 + * PLL_N = 432 * PLL_P = 2 * PLL_Q = 9 * VDD(V) = 3.3 @@ -244,13 +244,12 @@ WEAK void SystemClock_Config(void) __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); /* Initializes the RCC Oscillators according to the specified parameters */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; - RCC_OscInitStruct.PLL.PLLM = 8; - RCC_OscInitStruct.PLL.PLLN = 216; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 432; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLQ = 9; if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {