Experimental performance family (default-off): load-balance infrastructure, active-box windowing, block-structured AMR, hybrid WENO/Riemann sensors#1628
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…, correct growth comment)
…inal-review fixes)
…-IBM lib-4425 Commit 21d5965 declared the fine-IB AMR derived-type allocatables (ib_fine, ib_markers_save, ghost_points_save) inside module m_ibm. On CCE OpenMP/OpenACC offload this corrupts the declare-target descriptor table for m_ibm's ghost_points, aborting its @:ALLOCATE with lib-4425 (Uninitialized descriptor) even for a plain non-AMR IBM run that never touches the AMR state. Moving those declarations into a sibling module m_ibm_fine keeps m_ibm's compiled image identical to the pre-SP20 baseline. Pure module reorganization; numerically neutral. Plain IBM passes 6/6 (omp) and 3/3 (acc) deterministically on Frontier.
…ointer-swap) for Cray GPU The static-IB-AMR fine swap move_alloc'd/realloc'd/detach-attach'd the declare-target ghost_points and pointer-swapped + detach/attach'd the declare-target ib_markers to redirect them at each fine block. On Cray GPU (CCE OpenACC + OpenMP offload) these churn the device present table: ghost_points aborted with a present-table/lib-4425 crash (acc), and the ib_markers detach/attach left the marker descriptor pointing at the stale coarse array, corrupting the immersed-boundary correction on the fine block (~10% error; CPU was correct). Both declared arrays are now allocated once and never move_alloc'd/reallocated/pointer-swapped: the fine and coarse states are host-side copies parked in ib_fine slots (markers%sf and gps are host-only, no ACC_SETUP) and synced into the device-resident ib_markers/ghost_points via GPU_UPDATE. An extra ib_fine slot parks the coarse state; ib_markers is sized to the coarse bounds (a PROHIBIT guards fine<=coarse). No new module-level derived-type allocatable is added (that re-triggers the CCE descriptor-corruption lib-4425). Frontier: plain IBM + the 3 static AMR-IB goldens (2854A102, 7FC2F9F8, F980C769) now pass on both gpu-mp and gpu-acc, matching CPU. The moving-IB golden (13945217) still has a separate GPU-specific ~0.8% residual in the s_update_mib per-substep recompute (tracked separately).
…e interpolation In the AMR subcycle path s_update_mib is called with th>=0, which time-interpolates the moving body position on the host between its t^n snapshot and current position. But the RK body-motion update (m_time_steppers) writes patch_ib on the device, leaving the host copy stale, so on GPU the fine block was rebuilt at the stale t^n position (correct on CPU, where host==device). Add a GPU_UPDATE(host) before the interpolation. Reduces the moving-IB AMR golden error on Frontier; a small single-cell residual remains (GPU-vs-CPU boundary-cell classification for the moving body). Coarse/non-AMR moving IB is unaffected (called without th, no host read).
…ckends s_find_ghost_points builds the ghost-point list with a GPU atomic capture that assigns array slots in thread-completion order, so the list order is nondeterministic on the GPU and differs from the CPU's serial loop order. Order-sensitive work downstream (surface-force reduction; shared-cell access in the ghost-state correction), amplified by the discrete image-point stencil, then gave backend-dependent results. Only moving AMR-IB is affected: static AMR-IB and non-AMR moving IB never rebuild the list on-device every substep. Sort the list into deterministic lexicographic (i,j,k) cell order so every backend iterates identically (num_gps ~1e2, so the host round-trip is negligible). Fixes the moving AMR-IB golden divergence and the two-body NaN on gpu-mp and gpu-acc. Tests: place the moving bodies at generic off-grid-line centres (symmetric 0.5,0.5 puts image points exactly on cell boundaries - a knife-edge any discrete IB has, turning a 1-ULP host/device difference into a whole-cell flip). Two-body keeps a modest override_tol=1e-5 for the residual discrete sensitivity of its denser ghost interaction. Remove the dynamic-regrid moving-IB test: regrid box-tagging (a discrete >amr_tag_eps decision on the flow) plus the IB stencil give an irreducible ~1e-3 cross-backend difference no modest tolerance can capture.
…ing + right-sized memory (Phase 2) Redistribute the AMR fine level independently of the coarse decomposition: each block is owned WHOLE by a single SFC/work-balanced rank (amr_block_owner), so the fine work is load-balanced instead of pinned to the coarse-region owners. The three coarse<->fine couplings (coarse-patch gather, fine->coarse restriction scatter, Berger-Colella reflux) are converted from global collectives to owner<->SFC-local-neighbor POINT-TO-POINT via a replicated coarse-decomposition table (amr_decomp, allgathered once at init); the runtime device ghost-fill reads the gathered patch (amr_cg). Fine/coord/register arrays are right-sized to amr_maxc_fit (the max block a rank can own) so per-rank memory scales instead of holding a global-half block on every rank. Whole-block ownership drops the fine-fine continuation halo. VALIDATED: np=1 bit-identical across the AMR golden suite; np=2 conservation exact (machine zero).
… seam-exclusion + restart-with-tiling (Phase 3) Cover refined regions larger than a single rank's whole-block limit (amr_maxc_fit) by TILING them into contiguous <= amr_maxc_fit sub-blocks (s_amr_tile_box), each whole-owned by one rank - this also improves load balance (more, smaller blocks to distribute). Adjacent sub-blocks get a block-to-block fine-fine halo (s_amr_fine_fine_halo: buff_size-deep near-seam interior exchange between sub-block owners) so a seam ghost reads its neighbour's stage-entry interior; the fine advance is restructured into fill-all -> halo -> advance-all driver phases. Reflux excludes fine-fine seam faces (only true c/f faces reflux). Restart is a two-pass owner-before-geometry read (read regions -> assign owners -> place data) matching the init/regrid ordering, for both parallel_io and serial. CRITICAL ordering fix: s_amr_assign_block_owners runs BEFORE the owner-dependent s_set_amr_fine_geometry (a stale rank-0 owner map only surfaced with tiling's multi-block owners). VALIDATED: np=1 bit-identical; np=2 static tiled block + dynamic-regrid restart roundtrip conserve to machine zero.
… np>=2 correctness) The regrid overlap-copy that preserves a covering old block's fine detail (its stashed q_cons_stor) was LOCAL-ONLY. Under fine-level distribution an old block can be owned by a rank OTHER than the one now owning a covering new block, so the copy was silently skipped and the new block kept only its coarse-prolonged values - exact on uniform grids but ~O(1e-4) wrong on stretched grids where prolongation is inexact (the 79B334C7 failure). Migrate each covering old block's stashed fine state from its owner to the new-block owners that need it, keyed by region overlap; old_ilo/old_ext taken from the replicated GLOBAL region so the index shift is valid on every rank. VALIDATED -b mpirun: 79B334C7 (1D stretched dynamic-regrid, 2 ranks) passes; uniform + np=1 batch pass.
…k-splitting - The golden was generated on the mirror decomposition, which at np=1 CLAMPS a regrid box to amr_maxc_fit (<= half the domain per dim): B7704247's density tag grows to ~32 y-cells but the mirror refined only y4:23 (20 cells), leaving y24:35 coarse. Block-splitting TILES the box instead, refining the FULL tagged region (y4:19 + y20:35). So HEAD refines 12 extra y-cells the old golden left coarse - a real, intended solution change (more refinement), not a bug: HEAD-no-regrid is bit-identical to the mirror, conservation is exact, and the 1D seam is exact. np>=2 cases (5EFB3277/BD21A5C0) already pass because the mirror splits the block across ranks there = same footprint as tiling; only np=1 tags exceeding amr_maxc get more refinement from tiling. Regenerated with the tiled binary.
…golden regenerated); note amr_g?cb edge-ghost gap
…rature side-state coarse<->fine coupling (prolong + restriction, s_amr_prolong_pbmv / s_restrict_pbmv) reads/writes the block owner's LOCAL coarse pb/mv. Under fine-level distribution the SFC-assigned owner need not hold the block's coarse cells, so at np>=2 pb/mv couples to the wrong/stale coarse side-state - a silent wrong answer (q_cons is distributed via the P2P gather/scatter; pb/mv is not yet). Add a checker PROHIBIT (qbmm .and. .not. polytropic .and. num_procs>1) in the amr block of m_checker; remove the now-dead span-only gate in s_amr_compute_isect (it read the mirror isect - overwritten by s_set_amr_fine_geometry under whole-block - and only guarded the initial block, missing regridded ones; the checker gate is stricter and fires first). VALIDATED (isolated worktree, CPU reldebug): np=2 non-poly QBMM AMR aborts with the message; np=1 (8EDFC2F4/BCBA6E74/B0A5D230 physics) runs unchanged. No np>=2 QBMM+AMR golden exists, so nothing regresses. pb/mv gather/scatter = future work when np>=2 QBMM+AMR is needed + testable.
…gression) - s_restrict_fine_to_coarse (owner path) did GPU_UPDATE(host) the fine block -> restrict on HOST (s_amr_restrict_overwrite) -> GPU_UPDATE(device) the WHOLE coarse_tgt%sf. That whole-array push clobbered the device-advanced NON-COVERED coarse cells with the stale host copy: a GPU-only divergence (invisible on CPU where host==device) written straight into the coarse output (cons.1.00). ~1e-10 for stable physics, amplified to O(1e-2) by the IGR Jacobi solve / MHD / acoustic. New s_amr_restrict_overwrite_device (GPU_PARALLEL_LOOP collapse=4) restricts fine(device)->coarse(device) touching ONLY the covered cells - inlines f_amr_restrict_cell EXACTLY (same child-sum order + stp cast) so it is bit-identical to the host path on CPU and matches the coarse restriction. np=1 owner path is now device-native (no fine host-pull, no whole-coarse device push); keeps QBMM + rank_time; num_procs>1 keeps the existing host+P2P path. VALIDATED: gpu-mp -c phoenix full AMR set 42 passed / 2 failed (was ~1/21); the 2 remaining are unrelated (660FFBFE = the separate CPU 1e-9 IGR-regrid regression, now matching CPU; 79B334C7 = np>=2, not touched). CPU reldebug bit-identical: 21C71558/6C20B752(IGR)/73355E90(MHD)/ACE05393(hypoelastic) pass. REMAINING: extend device-native to the np>=2 local restriction (+ the gather) with host only for the cross-rank halo.
…er) - Extend the np=1 fix (d8f1c5c) to the np>=2 restriction scatter. Owner-local covered cells now restrict fine(device)->coarse(device) via s_amr_restrict_overwrite_device instead of s_amr_restrict_overwrite(host)+whole-coarse GPU_UPDATE(device); the receiver pushes ONLY its covered coarse section, not the whole array. Both whole-array device pushes clobbered the device-advanced non-covered coarse cells with a stale host copy - the same GPU-only bug fixed at np=1, invisible on CPU where host==device. Host round-trip remains only for the cross-rank MPI send-slice packing (all-on-gpu-except-halos). VALIDATED (Phoenix V100, gpu mp, clean build): 79B334C7 (np=2 stretched, was FAILING) + 5EFB3277 (np=2 dynamic regrid) + 21C71558 (np=1) all pass; CPU reldebug bit-identical. Also escape %% in amr_fine_distribution.md:133 for the doc-reference lint.
…for tiling - Same class as B7704247: the golden was generated on the mirror decomposition (up/mega 6f518df), which at np=1 CLAMPS a regrid box to amr_maxc_fit (<= half the domain per dim). 660FFBFE's dynamic tag grows to x3:46 (44 coarse cells on the 50-wide grid); the mirror clamps it to x3:27 (25 cells, DIRECTLY OBSERVED: mirror 58c1a0b prints 'block: box x 3:27 (25 coarse cells)') and leaves x28:46 coarse. Block-splitting TILES the box instead into x3:24 + x25:46, refining the FULL tagged region (HEAD prints 4 blocks). So HEAD refines x28:46 the old golden left coarse - the same real, intended more-refinement change, not a bug. EVIDENCE it is benign: (1) the mirror binary (58c1a0b, pre-tiling) PASSES the old golden bit-for-bit; (2) the field diff is spatially CONFINED to x-cells 28:48 = exactly the mirror's clamp-off region, and the left tile x3:24 matches the golden (a solver bug would perturb both tiles); (3) the ~1e-4 conservation defect is INHERENT to this IGR case - the STATIC twin 6C20B752 (single block, no tiling, passes its golden) shows the same-order defect (mass 2.7e-5 vs 7.9e-5), so tiling seams are not breaking conservation; (4) static IGR passes because it never re-tags past amr_maxc. Max diff 3.35e-3 in cons.3 (y-mom). Regenerated release (--no-gpu --no-debug) with the tiled binary; 6C20B752 unchanged.
…roadcast) - The regrid fine-state migration (an old block's stashed fine detail must reach whichever rank now owns a covering new block) was a collective MPI_Bcast of EVERY old block to ALL ranks - O(n_blocks x n_ranks) per regrid, the last global collective in the fine-level coupling. Now POINT-TO-POINT (mirrors s_amr_gather_coarse_patch): each old owner Isends its stashed q_cons_stor only to the DISTINCT new-block owners whose region overlaps that old block (f_amr_boxes_overlap on the replicated coarse boxes); receivers Irecv only the old blocks they need. Moved s_amr_assign_block_owners BEFORE the migration so the new owners are known when choosing destinations. A rank that did not receive old block kk never reads it - the overlap-copy's per-(k,kk) index guard skips every cell of a non-overlapping pair. Fine-level coupling is now fully P2P end to end (gather + restriction + reflux + migration); no per-regrid global collective remains. np=1 bit-identical (migration skipped under num_procs==1; the assign reorder is neutral - nothing between reads amr_block_owner). VALIDATED CPU reldebug -b mpirun: 79B334C7 (stretched np=2 dynamic regrid - the migration-correctness case, reverts to ~1e-4 if a needed block is not delivered) PASSES, plus 5EFB3277 + BD21A5C0 (np=2) and 21C71558 (np=1).
…_amr_restart (parallel_io) required the writing rank count; it now REPARTITIONS. Whole-block ownership makes each block's fine data one contiguous region-sized chunk at a computable offset - the only rank-count dependence in the file layout is the 3*np_old per-block extents record. So: read the writer's np_old from the header, use it for the file-layout strides (blk_base + data offset), re-assign block owners for THIS run via s_amr_assign_block_owners, and each new owner reads its whole blocks (the EXSCAN yields offset 0 for the block's sole current owner). The same-decomposition per-rank layout check is skipped when np_old /= num_procs (it cannot match by design; the end-of-read file-size check still fails closed on truncation/corruption). np_old == num_procs is byte-identical to the previous same-rank path. Serial (non-parallel_io) mode still needs the writing rank count (message now points to parallel_io for repartition). NO write-side change - existing checkpoints are already repartition-readable. VALIDATED CPU reldebug -b mpirun (1D AMR dynamic-regrid, save at step 3, restart 3->6): np=2->np=1 AND np=1->np=2 both print the repartition line, restore the fine level (2 blocks), and conserve (mass 8e-13 / energy 1e-12); 5EFB3277 (np=2 same-rank parallel restart) still passes.
…e_slot (no-op) - Foundation for lazy owned-only slot sizing (right-size a rank's fine memory to ~1/num_procs of the pool instead of all amr_max_blocks slots on every rank). Move the per-slot allocation (coords + the 6 device-resident field vectors + non-poly QBMM side-state) out of the init loop and the matching deallocation out of finalize into s_amr_alloc_slot(islot) / s_amr_free_slot(islot); promote the sizing locals (max_f1/2/3, mbuf1..3_lo/hi) to module scope so the helpers see them; add amr_slot_live(:) to track which slots are allocated. Init/finalize still call the helpers for EVERY slot, and the single QBMM RHS scratch (amr_rhs_pb_f/mv_f) is allocated once outside the per-slot helper - so this commit is bit-identical; the lazy reconcile at regrid/init/restart follows. VALIDATED CPU reldebug -b mpirun: 21C71558 + 6C20B752 (np=1 IGR) + 5EFB3277 (np=2) all pass.
…um_procs - Build on the alloc/free helpers (daa36af): a rank now allocates a slot's per-block field arrays (coords + the 6 device-resident field vectors + non-poly QBMM side-state, all sys_size x block) ONLY for blocks it owns, instead of all amr_max_blocks slots on every rank. s_amr_reconcile_slots allocates owned / frees the rest, called once ownership is known: init (after s_amr_assign_block_owners), restart (serial + parallel, before the owned read), and regrid. The regrid keeps the transient slots live across the critical section - old-owned (for the P2P migration SEND) + newly-owned (for the build) + received-old (alloc'd before the q_cons_stor unpack) - then reconciles to new-owned-only at the end, freeing the rest. Safe because every heavy-array access is ownership-guarded (fill/advance early-return on .not. amr_rank_owns_block), so an unowned/freed slot is never touched; np=1 owns all blocks so it is bit-identical (only the inactive pool slots beyond amr_num_blocks go unallocated). Per-rank fine memory now scales ~1/num_procs instead of num_procs x the data. (IB marker fields are allocated en masse by m_ibm and are per-cell integers, not sys_size x block - left global.) VALIDATED: CPU reldebug np=1 bit-identical (21C71558/6C20B752 IGR), np=2 (79B334C7 stretched regrid+migration, 5EFB3277, BD21A5C0 chem), repartition restart 2->1 conserves (mass 8e-13); GPU mp (Phoenix V100, clean build) 5/5 (21C71558/6C20B752/79B334C7/5EFB3277/660FFBFE) - device present-table consistent through the lazy alloc/free at regrid.
…pped) - The SFC map distributes WHOLE blocks, so with fewer blocks than ranks some ranks own no fine work - the fine-level load balance is capped at min(num_blocks, amr_max_blocks)/num_procs. Surfaced by the np>=4 load-balance demonstration: a concentrated region balanced PERFECTLY (1.00x imbalance, exact conservation) at np=4 (4 blocks) and np=8 (8 blocks with amr_max_blocks=16), but the default amr_max_blocks=4 capped np=8 at 4 blocks -> 2.0x. Add a rank-0 init warning when amr_max_blocks < num_procs pointing the user to raise it. np=1/small runs unaffected (fires only when num_procs > amr_max_blocks).
…-compiler flips The 4 hybrid-sensor golden tests at hybrid_weno_eps=0.5 (BA4340EA, 60739A3E and the AMR 053C5DDA, DDC4BA8A) failed on aggressive-optimizer lanes (intel no-debug, NVHPC 24.1/24.3, Frontier GPU) with percent-level LOCAL diffs. Root cause: the Jameson sensor's per-cell phi = |c+ - 2c0 + c-|/(|c+|+2|c0|+|c-|) is catastrophic cancellation at a shock, so a compiler's FP contraction/reordering jitters phi; where phi sits NEAR eps a cell flips between central and WENO -> a large local change. eps=0.5 sat at the edge of a plateau, ~0.001 from a shock cell at phi~=0.499. Fix is not a tolerance bump but a well-placed threshold. An eps-sweep of each exact case (run at many eps, diff outputs) shows the output is bit-identical across eps in [0.20, 0.40] -> no cell's phi lands in that band on ANY timestep = a clean phi GAP. eps=0.30 is centred there with a +/-0.10 margin: the full cross-compiler SOLUTION drift (~5e-4) moves phi only ~1e-3, ~100x inside the margin, so no compiler can flip a cell. The sensor still fires consequentially (answer moves ~4e-4 vs a dead all-WENO sensor, 7-10x the 5e-5 tol). Same gap holds for weno and riemann modes and on the AMR fine level (all measured). VALIDATED (Phoenix GNU CPU): 4/4 pass vs regenerated goldens under the normal build AND --fastmath (aggressive FP reordering). Robustness is by construction (measured phi gap); the intel/NVHPC-24.x lanes are the final confirmation in CI.
CCE OpenMP-offload never initializes the descriptor of the bare module-scope scalar_field allocatable amr_cg, so allocate(amr_cg) aborts with lib-4425 at startup - crashing every AMR case on gpu-mp/gpu-omp/AMD-flang. Allocate a local (which gets a valid descriptor) and move_alloc it into amr_cg, then map. OpenACC unaffected.
s_find_ghost_points assigns ghost-point slots via GPU atomic-capture (thread-completion order), which is nondeterministic; the order-sensitive surface-force reduction and the discrete image-point stencil then make moving AMR-IB diverge across backends. Sort the list on-device into lexicographic (i,j,k) order - no host round-trip, since a GPU_UPDATE here fails Cray's present-table lookup and this routine runs mid-swap in the AMR fine path. Also drops the routine's dummy argument to use the module-global ghost_points directly. Verified: tests/13945217 fails at 1e-10 without the sort, passes with it.
# Conflicts: # toolchain/mfc/test/cases.py
The AMR fine/coarse ghost-point swap copied the declare-target ghost_points through the host (GPU_UPDATE host -> host park -> GPU_UPDATE device) only because the parking storage ib_fine%gps was a plain host array. An audit confirmed the swap park is the ONLY host access of ghost_points: every consumer (correction kernel, s_find_ghost_points, levelset, image points, interpolation coeffs, moving recompute) runs on-device, the collision-forces ghost_points arg is dead, and there is no cross-rank exchange. Replace ib_fine%gps with a device-resident gp_park(:,:) and swap via on-device kernels, eliminating the host round-trip. gp_park is mapped dynamically with move_alloc + GPU_ENTER_DATA (the amr_cg idiom) so the bare derived-type allocatable gets a valid descriptor and device mapping without the CCE OpenMP-offload lib-4425 uninitialized-descriptor abort; a direct GPU_DECLARE + @:ALLOCATE would corrupt a sibling descriptor. ghost_point is trivially copyable, so the device struct assignment is well-defined. This supersedes the ghost_points(1:num_gps) slice band-aid: removing the whole-array ghost_points GPU_UPDATE also fixes the amdflang IBM+AMR offload crash (per-element custom mapper -> ROCm HSA OUT_OF_RESOURCES) at its source, without keeping the host round-trip. Verified 4/4 IBM-AMR cases (static + moving) on Frontier gpu-mp (CCE OpenMP-offload), gpu-acc (OpenACC), and CPU.
…FlowCode#1636) The AMR moving-IBM-circle test (13945217) ran a wall at vel=0.2 for 10 steps, long/fast enough to develop the spurious-pressure / CFL blow-up inherent to MFC's moving-IB method (no geometric-conservation-law treatment). The marginal instability NaNs on OpenMP-offload (CCE gpu-mp and amdflang) while passing on OpenACC and CPU. The real fix (a GCL/cut-cell treatment) is tracked in MFlowCode#1636 and deferred. Soften the case so it stays sub-marginal on all backends while still exercising the per-substage fine-IB recompute: slow the wall to vel=0.02 and stop at 4 steps (matching the two-body case's short-run pattern). Regenerated goldens. Verified 13945217 passes on gpu-mp (CCE OpenMP-offload), gpu-acc (OpenACC), and CPU.
…sent-table leak) s_amr_free_slot freed each slot's fields with @:DEALLOCATE only, but @:ACC_SETUP_SFs maps two things per scalar field on Cray - the descriptor ([arg]) and the field data ([arg%sf]) via GPU_ENTER_DATA copyin. Since Cray 'exit data delete' decrements the reference counter, the lone @:DEALLOCATE(arg%sf) undoes only the @:ALLOCATE create ref, leaving the descriptor and the ACC_SETUP %sf copyin ref dangling in the present table. Latent at program exit, but s_amr_free_slot frees slots MID-RUN (regrid / restart / reconcile), so the leaked host addresses get reused by the next allocation. On the AMR restart path the reused address is Gs_rs (Riemann init runs after s_read_amr_restart frees the init slot), tripping 'CRAY_ACC_ERROR - Error placing gs_rs: another instance already present' and killing the run (test 5EFB3277, AMR 1D dynamic regrid, 2 MPI ranks, gpu-acc). Add @:ACC_TEARDOWN_SFs (exact inverse of @:ACC_SETUP_SFs) and call it before each field's @:DEALLOCATE in s_amr_free_slot so every ACC_SETUP enter is matched by a delete. Cray-only (#ifdef _CRAYFTN), so non-Cray is unchanged. Verified 5EFB3277 passes on gpu-acc (2 ranks + restart roundtrip) and CPU.
The single-body moving-IBM case (13945217) was slowed to vel=0.02 in 4c877aa to dodge the un-GCL'd blow-up (MFlowCode#1636). The two-body case is pushed on top of it in the CaseGeneratorStack WITHOUT a pop, so it inherited that change - silently dropping body 1's wall speed 0.2 -> 0.02 and invalidating 43AF9F25's golden (which was generated at 0.2). That regressed 43AF9F25 across all backends (the softened setup diverges more on CPU than on GPU, hence the confusing CPU 91% vs gpu-acc 1.4x-tol spread). Restore body 1's vel=0.2 in the two-body push so the softening stays scoped to 13945217. 43AF9F25 is unchanged from its known-good config; no golden regen. Verified 43AF9F25 passes against its existing golden on CPU, gpu-mp (CCE OpenMP-offload), and gpu-acc (OpenACC).
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Summary
An opt-in, default-off family of performance features and the measurement infrastructure they rest on. With all flags at their defaults the only touched production path is
s_mpi_decompose_computational_domain, refactored through the newm_boxmodule (byte-identical; covered by the existing suite).m_box(partition arithmetic),m_load_weight/load_weight_wrt(per-cell load-weight field + imbalance metric),m_sfc_partition/sfc_partition_wrt(Morton-SFC predicted-imbalance diagnostic),m_load_balance/load_balance(weighted static decomposition at init; AMR-fine-work-aware),m_rank_timing/rank_time_wrt(per-rank compute-time diagnostic).m_active_box/active_box: restricts reconstruction/Riemann/RK windows to a light-cone-grown box around non-ambient flow; strict-subset golden-tested.hybrid_wenoandhybrid_riemann(+hybrid_weno_eps,hybrid_smooth_flux): linear-optimal weights / central-or-Rusanov flux in smooth cells, full WENO/HLLC at flagged discontinuities (Jameson sensor, stencil-dilated, per-level under AMR).m_amr+m_amr_registers: two-level 2:1 refined block hierarchy; conservative restriction and conservative-linear prolongation with physics-specific closures; per-stage flux registers with Berger–Colella refluxing; Berger–Rigoutsos multi-block dynamic regrid; optional dt/2 subcycling; multi-rank (blocks may span rank seams; fine halo exchange; distributed registers); restart (both IO modes, regridded-layout persistence); AMR-aware post-processing (fine blocks visualizable as Silo overlay domains); GPU-resident fine level on both OpenACC and OpenMP offload.Full algorithm and user documentation:
docs/documentation/amr.md(support matrix enforced at runtime by the checker — unsupported combinations abort with named messages, never silently).AMR physics support matrix (abridged; authoritative table in amr.md)
Supported and golden-tested: single- and multi-fluid (5-eq,
mpp_lim) · 6-eq with per-block pressure relaxation · viscous (refluxed) · phase change (relax) · chemistry incl. species diffusion · Euler–Euler bubbles (polytropic/non-polytropic, mono/polydisperse, QBMM incl. non-polytropic with per-blockpb/mvside-state; dynamic regrid + subcycle) · acoustic sources (coarse-grid support with regrid exclusion) · immersed boundaries (multi-body, static or prescribed-motion, incl. dynamic regrid with body-containment expansion and per-substage guards) · 2D axisymmetric (per-block WENO-coefficient recompute) · stretched grids (exact parent-bisection ghost coordinates + per-swap coefficient recompute) · hybrid WENO/Riemann sensors (per-level) · Lagrangian bubbles (cloud excluded from blocks; two-way coupling on the coarse grid; regrid clips around the moving cloud) ·active_box(blocks contained in the growing window; agrees with plain AMR to ~1e-14) · IGR (restriction-only coupling: fine sigma solve seeded/Dirichlet-bounded by the coarse solve; documented truncation-order seam, exact free-stream) · 1D MHD/RMHD (div(B)=0 by construction in 1D; HLL and HLLD, incl. relativistic).Gated with named aborts (documented rationale): surface tension (seam force imbalance is structural — three fixes attempted and diagnosed in amr.md) · 2D/3D MHD (attempted and measured: the c/f seam is a continuous O(1) div(B) source GLM cleaning cannot remove — needs constrained-transport-class B prolongation/reflux) · hyperelasticity · 3D cylindrical (global azimuthal filter) · force-driven IB (
moving_ibm=2) · STL bodies · Riemann-extrapolation BCs (bc=-4) ·amr_subcycleunder IGR · stretched grids with Lagrangian/IB-regrid (uniform-spacing index conversions).Validation evidence
Known issues (all non-gating or in progress)
continue-on-error): an intermittent post-detected NaN on the two Lagrangian+AMR goldens. Exhaustively unreproducible off GitHub's runners — the exact failing stack (NVHPC 24.3 SDK,-tp=px -Kieee, HPC-X MPI, and the CI docker image itself under apptainer) passes elsewhere, as do native/zen2 builds; 24.5+ green. Documented at the golden definitions.Review guide
The commit history is arc-ordered (active-box → load-weight → SFC → weighted decomposition → rank timing → hybrid → m_box → AMR rungs → physics envelope → CI/GPU hardening); reviewing by arc is much easier than by file. The AMR arc builds stepwise: static hierarchy → restriction/prolongation → fine advance → refluxing → regrid → subcycling → multi-rank → GPU → each physics rung with its own validation. Commit messages carry the validation evidence for their change (measured defects, golden UUIDs, repro details for CI fixes).
All parameters ship default-off with
case_validatorentries, runtime checker gates, andcase.md/amr.mddocumentation.