🚀 Memory Management Unit (MMU) Design Using Verilog HDL

📖 Overview

This project implements a 32-bit Memory Management Unit (MMU) in Verilog HDL capable of translating virtual addresses into physical addresses using a Translation Lookaside Buffer (TLB) and a Page Table Walker (PTW).

The MMU supports:

• Virtual-to-Physical Address Translation
• TLB-Based Address Lookup
• Page Table Walking (PTW)
• Permission Checking
• Execute Fault Detection
• Bypass Mode Operation
• Verification using Icarus Verilog and GTKWave

This project demonstrates key concepts in Computer Architecture, Memory Management, RTL Design, and Digital System Verification.

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✨ Features

• ✅ 32-bit Virtual Memory Translation
• ✅ Translation Lookaside Buffer (TLB)
• ✅ Page Table Walker (PTW)
• ✅ Permission Checking
• ✅ Execute Fault Detection
• ✅ TLB Refill Mechanism
• ✅ Physical Address Generation
• ✅ Bypass Translation Mode
• ✅ Self-Checking Testbenches
• ✅ GTKWave Verification

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🏗️ MMU Architecture

Major Components

TLB (Translation Lookaside Buffer)

• Stores recent address translations
• Performs VPN + ASID matching
• Provides fast translation lookup

PTW (Page Table Walker)

• Handles TLB misses
• Reads page table entries from memory
• Extracts PPN and permission bits

Permission Checker

• Read Permission Validation
• Write Permission Validation
• Execute Permission Validation
• User/Supervisor Access Checking

Physical Address Generator

Generates:

Physical Address = {PPN, Offset}

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📂 Project Structure

MMU-Design-Verilog-HDL
│
├── docs
│   └── MMU_Project_Documentation.md
│
├── images
│   ├── bypass_mode.png
│   ├── execute_fault.png
│   ├── mmu_architecture.png
│   ├── mmu_waveform.png
│   ├── tlb_hit.png
│   └── tlb_miss_refill.png
│
├── reports
│   └── Verification_Report.md
│
├── rtl
│   ├── mmu.v
│   ├── perm_check.v
│   ├── ptw.v
│   └── tlb.v
│
├── tb
│   ├── mem_bram.v
│   ├── mem_bram_tb.v
│   ├── mmu_tb.v
│   ├── perm_check_tb.v
│   ├── ptw_tb.v
│   └── tlb_tb.v
│
├── .gitignore
├── LICENSE
└── README.md

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🧠 Address Format

Virtual Address (32-bit)

31                     12 11          0
+-----------------------+-------------+
| Virtual Page Number   |   Offset    |
+-----------------------+-------------+
         20 bits            12 bits

Physical Address (32-bit)

31                     12 11          0
+-----------------------+-------------+
| Physical Page Number  |   Offset    |
+-----------------------+-------------+
         20 bits            12 bits

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⚙️ Simulation

Compile

iverilog -g2012 -o mmu_test \
tb/mmu_tb.v \
tb/mem_bram.v \
rtl/mmu.v \
rtl/tlb.v \
rtl/ptw.v \
rtl/perm_check.v

Run

vvp mmu_test

Open Waveforms

gtkwave mmu.vcd

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📊 Simulation Waveform

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🧪 Verification Results

Test 1 — TLB Miss + Refill

Result:

PA = 00ABC100

✅ PASS

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Test 2 — TLB Hit

Result:

PA = 00ABC200

✅ PASS

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Test 3 — Execute Fault Detection

Result:

exec_fault = 1

✅ PASS

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Test 4 — Bypass Mode

Result:

PA = CAFEBABE

✅ PASS

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📈 Final Simulation Output

TEST1 : TLB MISS + REFILL
PA=00abc100

TEST2 : TLB HIT
PA=00abc200

TEST3 : EXECUTE FAULT
exec_fault=1

TEST4 : BYPASS
PA=cafebabe

MMU TEST COMPLETE

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🛠 Tools Used

Tool	Purpose
Verilog HDL	RTL Design
Icarus Verilog	Simulation
GTKWave	Waveform Analysis
Git	Version Control
GitHub	Repository Hosting
VS Code	Development Environment

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📚 Learning Outcomes

• Memory Management Concepts
• Virtual Memory Translation
• Translation Lookaside Buffers (TLB)
• Page Table Walking (PTW)
• Permission Checking Logic
• RTL Design Methodology
• Functional Verification
• Waveform Debugging
• Digital System Design

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🔮 Future Enhancements

• 4-Way Set Associative TLB
• Multi-Level Page Tables
• TLB Replacement Policies
• RISC-V Sv32 Integration
• Performance Counters
• FPGA Deployment
• AXI Memory Interface

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📄 Documentation

Detailed documentation:

docs/MMU_Project_Documentation.md

Verification report:

reports/Verification_Report.md

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👩‍💻 Author

Vaishnava Devi

B.Sc. Digital and Cyber Forensic Science

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📜 License

This project is licensed under the MIT License.