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  1. RISC-V-Pipelined-Processor-Verilog- RISC-V-Pipelined-Processor-Verilog- Public

    5-Stage RISC-V Pipelined Processor designed in Verilog HDL featuring Instruction Fetch, Decode, Execute, Memory Access, and Write-Back stages with RTL simulation and verification.

    Verilog

  2. 4bit-processor-verilog 4bit-processor-verilog Public

    4-bit Processor designed in Verilog HDL featuring Fetch, Decode, Execute and Write-Back stages with ALU operations, register file implementation, simulation, and FPGA synthesis using Xilinx Vivado.

    Verilog

  3. DecodeLabs-IoT-Internship DecodeLabs-IoT-Internship Public

    Collection of IoT and Embedded Systems projects developed during the DecodeLabs Internship using ESP32, sensors, cloud connectivity, and real-time monitoring applications.

    C++

  4. elevator_using_sv elevator_using_sv Public

    FSM-based Elevator Controller implemented in SystemVerilog with functional verification using Xilinx Vivado.

    SystemVerilog

  5. uart-transceiver-verilog uart-transceiver-verilog Public

    UART Transceiver (TX/RX) implemented in Verilog HDL using 8N1 protocol with Vivado simulation.

    Verilog