PAP-RISC-V-CPU-VERILOG

Simple RISC-V CPU with 5-stage pipeline created as semestral work at FEE CTU.

Supports RV32I, hazard detection and forwarding.

Tested on gcc crosscompiled Stein's GCD algorithm implemented in RV assembly.

Created as part of Advanced Computer Architectures course led by Ing. Pavel Pisa PhD. at FEE CTU.