feat(v2.1): switch to checkpointed preflight with rvr - #3074
Draft
shuklaayush wants to merge 196 commits into
Draft
feat(v2.1): switch to checkpointed preflight with rvr#3074shuklaayush wants to merge 196 commits into
shuklaayush wants to merge 196 commits into
Conversation
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
This comment has been minimized.
shuklaayush
force-pushed
the
feat/rvr-preflight
branch
from
July 30, 2026 07:06
8c9d578 to
150229e
Compare
Contributor
Note: cells_used metrics omitted because CUDA tracegen does not expose unpadded trace heights. Commit: 150229e |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
On
develop-v2.1.0, execution and trace generation are coupled. Each instruction is executed by the chip that will later prove it, and that chip appends its own records as it runs. GPU trace generation then turns those records into trace rows:This PR splits the old preflight phase into CPU preflight and GPU postflight:
CPU preflight remains serial: it executes one instruction at a time against mutable VM memory. With the
rvrfeature, the compiled executor emits two arrays as it runs, checkpoints taken at a fixed interval and an ordered list of values called residuals, both defined below. GPU postflight re-executes the interval between each pair of checkpoints and builds one shared history that no later stage modifies. The interpreter writes that same history directly. Every trace generator reads it, after execution has finished.Execution modes
All three modes execute the same opcode implementations and differ only in what they retain:
Metering chooses the segment boundaries before any proving happens. Preflight executes exactly one of those segments, so the data it retains is bounded by what metering already measured.
How it works
The GPU receives a copy of memory before serial execution begins modifying it. Replay and indexing both treat that copy as the value of memory at the start of the segment, and neither writes to it.
What is recorded
A memory-derived residual is what advances replay. The same access also appears as an event in the memory log, and the memory index validates that event against the start-of-segment copy of memory and against the earlier events for that block. The value is therefore consumed by one mechanism and checked by another.
The compiled path's entire output is those two append-only arrays, checkpoints and residuals. Nothing about AIRs or chips appears until postflight has built the shared history, at which point trace generators select the opcodes they own and emit rows.
Postflight and trace generation
Postflight makes two passes over the intervals. The first counts how many events each interval produces, so the output buffers can be allocated at exactly the right size; the second writes the program and memory logs, with the intervals running in parallel. Both backends then build the memory and opcode indexes described above.
This history is where the two execution paths meet. CPU and CUDA build it with separate code, but they check the same things and hand trace generation the same information.
The system, RV64, and extension trace generators locate their instructions through the opcode index and build their rows from four inputs: the instruction as it appears in the program, the program log, the memory log, and the memory index. None of these change while trace generation reads them. Side effects such as reading a host hint occur once, during serial preflight; replay consumes the values they produced and never repeats them. One instruction can feed more than one trace, because executing an opcode is now independent of which chip owns the trace.
The buffers used for replay, sorting, and indexing are released after trace generation and before STARK proving. With them released, proving remains the phase that uses the most GPU memory.
Reuse across proofs
The compiled metering executor, the compiled preflight executor, and the copy of the program on the GPU depend only on the guest program, not on its input. They are prepared once and reused across proofs. Compilation is reported under its own one-time preparation metric, and the per-proof timer starts after preparation.
Each proof then runs:
Validation
The default Reth benchmark for block
24001988completed across 65 segments:Everything before backend proving took 4.326s: uploading the starting memory, preflight, postflight, trace generation, and the surrounding bookkeeping.
Resolves INT-8800