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Merged
shuklaayush merged 2 commits into from
Jul 16, 2026
Merged

feat: add zicclsm and unaligned scalar mem target features #4

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d21ea4d
feat: add zicclsm and unaligned scalar mem target features
mansur20478 Jul 15, 2026
46b4c0d
feat: enable linker relaxation for OpenVM target
shuklaayush Jul 16, 2026
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4 changes: 2 additions & 2 deletions compiler/rustc_target/src/spec/targets/riscv64im_unknown_openvm_elf.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@ pub(crate) fn target() -> Target {
data_layout: "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128".into(),
llvm_target: "riscv64".into(),
metadata: TargetMetadata {
description: Some("OpenVM zero-knowledge Virtual Machine (RV64IM ISA)".into()),
description: Some("OpenVM zero-knowledge Virtual Machine (RV64IM_ZICCLSM ISA)".into()),
tier: Some(3),
host_tools: Some(false),
std: Some(true),
Expand All @@ -29,7 +29,7 @@ pub(crate) fn target() -> Target {
max_atomic_width: Some(64),
atomic_cas: true,

features: "+m".into(),
features: "+m,+zicclsm,+unaligned-scalar-mem,+relax".into(),
llvm_abiname: "lp64".into(),
executables: true,
panic_strategy: PanicStrategy::Abort,
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15 changes: 7 additions & 8 deletions src/doc/rustc/src/platform-support/riscv64im-unknown-openvm-elf.md
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Expand Up @@ -2,7 +2,7 @@

**Tier: 3**

Target for [OpenVM](https://github.com/openvm-org/openvm/) virtual machines with the RV64IM ISA and custom RISC-V extensions defined through OpenVM's extension framework.
Target for [OpenVM](https://github.com/openvm-org/openvm/) virtual machines with the RV64IM_ZICCLSM ISA and custom RISC-V extensions defined through OpenVM's extension framework.

## Target maintainers

Expand Down Expand Up @@ -35,9 +35,10 @@ default allocator. Partial support for the Rust `std` library is provided using
Further commentary and the `openvm` crate's higher-level I/O helpers are documented in the [OpenVM book](https://docs.openvm.dev/book/writing-apps/writing-a-program#rust-std-library-support).

The target's execution environment is single-threaded, non-preemptive, and does not support
privileged instructions. At present, unaligned accesses are not supported and will result in execution traps. The binaries expect no operating system and can be thought
of as running on bare-metal. The target does not use `#[target_feature(...)]` or
`-C target-feature=` values.
privileged instructions. Misaligned scalar loads and stores are supported. The binaries expect no
operating system and can be thought of as running on bare-metal.

The target enables the LLVM features `+m,+zicclsm,+unaligned-scalar-mem,+relax` by default.

Binaries are expected to be ELF.

Expand Down Expand Up @@ -97,10 +98,8 @@ The target currently does not support running the Rust test suite.

## Cross-compilation toolchains and C code

Compatible C code can be built for this target on any compiler that has a RV64IM
target. On clang and ld.lld linker, it can be generated using the
`-march=rv64im`, `-mabi=lp64` with llvm features flag `features=+m` and llvm
target `riscv64-unknown-none`.
Compatible C code can be built with Clang and ld.lld using
`--target=riscv64-unknown-none -march=rv64im_zicclsm -mabi=lp64 -mno-strict-align -mrelax`.

[RISC-V specification]: https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf
[OpenVM]: https://github.com/openvm-org/openvm/
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