Add GIC and SMP examples to the Xilinx Zynq-A9

[sriramster]

xlinx-zynq-a9 example to demonstrate the SMP ability. The enable SMP we develop the GIC, the GIC implementation is derived from arm_gic::v2 which is a superset of v1 & v2 together as defined here, https://developer.arm.com/documentation/198123/0302/What-is-a-Generic-Interrupt-Controller-

• Add building an for the
  memory-mapped GIC. PERIPHBASE is hardcoded to 0xF8F0_0000 (fixed for
  this SoC) rather than read from CBAR, because
  issues the Cortex-R52 CBAR encoding, which is undefined on the A9.
• The example runs its SGI in Group 0: on this GIC (which reports the
  Security Extensions) only enables Group 0 on the CPU
  interface, so it also enables Group 0 in the Distributor and uses that
  group for configure/ack/EOI.
• The SMP example boots the second core and checks atomics and a cross-core critical section. Each core enables its own MMU.

[sriramster]

@thejpster the PR depends #205 .

[thejpster]

I think you need a toolchain file to get the rustup target installed?

[sriramster]

Did you mean, I don't need a toolchain inside the examples? I see that is how the other examples are written. The work with the root toolchain file. Let me remove the toolchain file and re-run the local tests once.

[sriramster]

Done, removed the example specific toolchain file. The PR depends on 205 that is the CI failures, as I built it ontop of 205 and things work there.

[thejpster]

I think your SMP test failed because both cores printed simultaneously. To help the tests be more deterministic it's probably best to have the cores only run one at a time

Core 1	Core 2
Boots	Parked
Unparks Core 2	Parked
Waits	Boots
Waits	Pings Core 1
Does stuff	Waits
Pings Core 2	Waits
Waits	Does stuff
Waits	Pings Core 1
Exits	Exits

[thejpster]

And feel free to rebase on #205 if you require it

[sriramster]

I have rebased to #205 all checks pass. @thejpster please have a look.

[thejpster]

LGTM but someone else needs to merge #205 first