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fix(solis): don't force TOU bit on CID 636 when no V2 slot is active#4239

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springfall2008 merged 1 commit into
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fix/solis_mode
Jul 12, 2026
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fix(solis): don't force TOU bit on CID 636 when no V2 slot is active#4239
springfall2008 merged 1 commit into
mainfrom
fix/solis_mode

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Summary

  • On V2-mode Solis inverters (per-slot CIDs), write_time_windows_if_changed always forced the storage-mode TOU bit (bit 1 of CID 636) on when choosing Self-Use/Feed-in-priority, regardless of whether slot 1 actually has a charge or discharge window configured.
  • The physical inverter only retains that bit when a schedule is actually active, and silently clears it on read-back otherwise — this produced a permanent write/verify-fail loop (Failed to verify CID 636 storage mode ..., wrote 35 but read back 33) every cycle once both charge and discharge were disabled for slot 1.
  • The V1 branch already has the correct behaviour (in_charge_slot or in_discharge_slot gating, falling back to the "... - No Timed Charge/Discharge" mode variant). This mirrors that same gating into the V2 branch, based on whether slot 1 has any enabled window.
  • Cross-checked storage-mode bit numbering, CID 636, and the V2 per-slot CIDs against the independent mkuthan/solis-cloud-control integration — identical mapping. That project also deliberately withholds manual TOU-bit control specifically for TOU-V2 inverters, corroborating that this bit shouldn't be forced by client code on V2.

Test plan

  • Added test_write_time_windows_v2_no_active_slot regression test (confirmed it fails against the old code, passes after the fix)
  • ./run_all --test solis — full Solis suite passes
  • pre-commit run (ruff, black, cspell) passes on changed files

🤖 Generated with Claude Code

The inverter only retains the TOU-mode bit (bit 1) on storage mode CID 636
when a charge/discharge window is actually configured; with no active slot
it silently clears the bit on read-back. The V2 branch of
write_time_windows_if_changed always forced that bit on regardless of slot
state, causing a permanent write/verify-fail loop every cycle once both
charge and discharge were disabled. Mirror the V1 branch's existing
in_charge_slot/in_discharge_slot gating: fall back to the
'... - No Timed Charge/Discharge' mode variant when slot 1 has no enabled
window.

Cross-checked bit numbering, CID 636, and the V2 slot CIDs against the
independent mkuthan/solis-cloud-control integration - identical mapping,
and that project likewise withholds manual TOU control on TOU-V2 inverters.

Co-Authored-By: Claude Sonnet 5 <noreply@anthropic.com>
Copilot AI review requested due to automatic review settings July 12, 2026 18:40

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Pull request overview

This PR fixes a Solis TOU-V2 edge case where Predbat could repeatedly fail to verify CID 636 (storage mode) after disabling slot 1 charge/discharge, because the inverter won’t retain the TOU bit unless a schedule is actually configured. The change aligns TOU-V2 behavior with the existing V1 gating, preventing a write/verify-fail loop when no slot is active.

Changes:

  • Track whether Solis TOU-V2 slot 1 has any enabled charge/discharge window and gate the storage-mode selection accordingly (use the ... - No Timed Charge/Discharge variants when inactive).
  • Add a regression test covering the “V2 mode, no active slot 1” scenario to prevent reintroducing the CID 636 verify-failure loop.

Reviewed changes

Copilot reviewed 2 out of 2 changed files in this pull request and generated no comments.

File Description
apps/predbat/solis.py Gates TOU-bit-bearing storage-mode variants in TOU-V2 based on whether slot 1 is enabled, avoiding perpetual CID 636 verify failures when no schedule is active.
apps/predbat/tests/test_solis.py Adds test_write_time_windows_v2_no_active_slot regression test and wires it into the Solis test runner.

@springfall2008 springfall2008 merged commit e4b66c6 into main Jul 12, 2026
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@springfall2008 springfall2008 deleted the fix/solis_mode branch July 12, 2026 19:38
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2 participants