32-bit Floating Point ALU (IEEE-754) – Verilog Implementation

Project Overview

This project implements a 32-bit Floating Point Arithmetic Logic Unit (FP-ALU) using Verilog HDL, compliant with the IEEE-754 single-precision format. The design supports core arithmetic operations including:

• Addition
• Multiplication
• Division

The architecture is modular, synthesizable, and verified using a self-checking testbench.

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Architecture

Top Module: fp_alu_top

The top-level module integrates three independent floating-point units:

• fp_adder
• fp_multiplier
• fp_divider

All units operate in parallel, and a multiplexer selects the output based on the operation code.

Operation Encoding:

op_code	Operation
00	Addition
01	Multiplication
10	Division

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Module Descriptions

1. Floating Point Adder (fp_adder)

• FSM-based multi-cycle design

• Stages:

  • Operand alignment
  • Addition/Subtraction
  • Normalization

• Handles:

  • NaN
  • Infinity
  • Zero

• Limitations:

  • No rounding logic
  • Incomplete normalization for subtraction

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2. Floating Point Multiplier (fp_multiplier)

• 3-stage FSM design:

  • Initialization
  • Mantissa multiplication
  • Normalization

• Uses 24×24-bit multiplication

• Handles special cases:

  • NaN
  • Infinity × Zero

• Limitations:

  • No rounding (truncation used)
  • No denormal handling

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3. Floating Point Divider (fp_divider)

• Multi-cycle FSM with restoring division

• Performs iterative mantissa division (24 cycles)

• Handles:

  • Divide-by-zero
  • NaN
  • Infinity

• Limitations:

  • Incomplete normalization
  • No rounding support
  • Denormals not supported

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Data Flow

1. Inputs (op_a, op_b) are fed to all units in parallel
2. Each unit computes independently
3. Output is selected using op_code
4. Results are registered for timing stability

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Exception Flags

Bit	Description
0	Invalid Operation
1	Divide by Zero
2	Overflow
3	Underflow
4	Inexact

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Testbench (fp_alu_top_tb)

Features:

• Self-checking testbench
• Task-based stimulus generation
• Automatic PASS/FAIL reporting
• Waveform dumping (VCD)

Test Coverage:

• Basic arithmetic operations
• Zero handling
• Infinity operations
• NaN propagation
• Overflow conditions
• Sign combinations

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Timing Constraints

SDC constraint used:

create_clock -period 10.000 -name clk -waveform {0 5} [get_ports clk]

• Clock frequency: 100 MHz
• Duty cycle: 50%

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Tools Used

• Verilog HDL
• AMD Vivado (Simulation & Synthesis)

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Design Characteristics

Feature	Description
Data Width	32-bit IEEE-754
Architecture	Modular FSM-based
Execution Type	Multi-cycle
Parallel Units	Yes
Output Register	Yes

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Applications

• DSP systems
• Scientific computation
• Embedded processors
• Hardware accelerators

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Conclusion

This project demonstrates a modular and scalable floating-point ALU design using Verilog, covering key arithmetic operations with FSM-based control. While functionally correct for most standard cases, further enhancements are required for full IEEE-754 compliance and high-performance applications.

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