Design and implementation of an IEEE-754 single-precision Floating-Point ALU using Verilog HDL
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Updated
Jun 16, 2026 - Verilog
Design and implementation of an IEEE-754 single-precision Floating-Point ALU using Verilog HDL
A 32-bit CPU in MIPS architecture
The algorithm proposes a prototype to design a 32-bit processor. The processor is capable of performing the task which includes fetching the instructions, decoding the instructions to figure out what operation needs to be performed, on what operands it needs to perform and where to store, write, the result obtained.
This is a 32 Bit Processor design with 3 address format and indirect addressing for my computer organization and architecture course
Simulating a 32-bit processor using VHDL
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