Remove unnecessary slice (s) LogicNets from sign_extended and zero_extended. - #496
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Codecov Report✅ All modified and coverable lines are covered by tests. Additional details and impacted files@@ Coverage Diff @@
## development #496 +/- ##
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- Coverage 93.8% 93.8% -0.0%
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Files 30 30
Lines 7143 7148 +5
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+ Hits 6694 6698 +4
- Misses 449 450 +1 ☔ View full report in Codecov by Harness. 🚀 New features to boost your workflow:
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…zero_extended`.
This removes 9% of pyrtlnet's slice (`s`) `LogicNets`, and 6% of pyrtlnet's
wire (`W`) `WireVectors`, without introducing new `LogicNets` or `WireVectors`.
This slightly speeds up simulations.
* Remove visualization special cases for bit-slices that select the same bit
multiple times. This case is now extremely rare now that `sign-extended`
`concats` multiple copies of the most significant bit.
* Move `output_to_verilog`'s logic for repeated bit seletions to concat ("c").
This generalizes the logic, so we now use the Verilog replication operator
for any repeated concat args, not just single-bit slices.
* Add a `FastSimulation` test for a non-consecutive bit-slice. We lost test
coverage for this case because `sign_extended` no longer generates slices
that copy the most significant bit.
* Add a sign_extended test that attempts to reduce bitwidth.
* Fix tests broken by this change and remove empty test methods.
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This removes 9% of pyrtlnet's slice (
s)LogicNets, and 6% of pyrtlnet's wire (W)WireVectors, without introducing any newLogicNetsorWireVectors. This speeds up simulation times, especially withpyrtl.Simulation.Fix tests broken by this change.