⚡ MobileNet-RTL: High-Performance Hardware Accelerator

📌 Overview

This repository contains a Verilog/SystemVerilog implementation of MobileNet-RTL, a highly optimized hardware accelerator designed for end-to-end inference of MobileNet-style workloads on edge FPGAs.

This project was submitted to the DVCon India 2026 Design Contest, achieving a placement in the Top 100 Nationwide.

The accelerator evaluates feature maps using a heavily pipelined custom Systolic Array and features intelligent Depthwise Convolution mapping, on-the-fly Global Average Pooling, and a built-in Semantic Scorer.

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📐 Architecture Diagram

graph TD
    A[Image Data] --> B(Window Generator)
    B --> C(Conv2D Mapper)
    C -->|Skewed Activations| D{9x16 Systolic Array}
    W[Weight Buffer] -->|Lookahead Load| C
    D -->|Spatial Accumulation| E(Global Average Pool)
    E --> F(Semantic Scorer)
    T[Task Embeddings] --> F
    F -->|Confidence Scores| G(Top-K Selector)
    G --> H[Final Classification]
    
    style D fill:#f9f,stroke:#333,stroke-width:2px
    style G fill:#bbf,stroke:#333,stroke-width:2px

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📊 Hardware Utilization & Metrics

Synthesized and evaluated with a 5.0ns Target Clock Period (200 MHz). The results demonstrate a highly efficient compute mechanism with a lightweight hardware footprint and excellent thermal characteristics under heavy loads.

Metric	Measured Value	Notes
Max Frequency (Fmax)	207.13 MHz	Positive slack (WNS: 0.172 ns)
Peak Compute Performance	106.05 GOPS	Utilizing the 16x16 Systolic Array
Estimated Layer Latency	0.943 ms	Assuming 100M ops/layer
Typical Power (50% Load)	0.752 W	Extremely power efficient for Edge
Peak Power (100% Load)	0.815 W	Max Junction Temp of 26.8 °C

Note: The system maintains thermal stability through dynamic clock gating triggered by the integrated Thermal Management Unit (TMU).

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✨ Key Features

✔ Custom Systolic Array Core

• 9x16 PE Array: Features 8-bit sparse MAC processing elements perfectly sized for mobile inference.
• Hybrid Stationary Design: The array dynamically switches between Weight-Stationary Convolution and Output-Stationary GEMM modes depending on the layer type.

✔ Advanced Memory Mitigation

• On-the-fly Global Average Pooling: Computes spatial accumulations internally and drains directly into the pooling module, eliminating the bandwidth overhead of writing feature maps back to memory.
• Lookahead Weight Loading: Uses a ping-pong buffer mechanism to stream weights for the next channel while computing the current one, achieving near 100% compute utilization in Depthwise Mode.

✔ Embedded Classification

• Semantic Scorer: Integrated pipelined hardware directly scores pooled feature vectors against 14 distinct task embeddings.
• Top-K Selector: Hardware-accelerated sorting to instantly determine the highest confidence classifications with zero latency overhead.

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🚀 Verification & Results

The complete pipeline has been rigorously tested using comprehensive trace-replay methodologies and PyTorch golden models.

Simulation Environments:

• scripts/run_tests.sh: The main regression suite. It compiles all RTL modules with Icarus Verilog (iverilog), verifies module-level unit tests, and orchestrates the full system-level inference across tb_MobileNet_Accelerator_System.v.
• tb_MobileNet_Accelerator_Validation.v: Validates the depthwise convolution performance scaling matrix across 16 up to 128 channels.
• src/golden_model.py: PyTorch script to generate the exact golden truth reference vectors used by the testbenches.

How to Run Verification: Navigate to the root directory and execute bash scripts/run_tests.sh.

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📂 Directory Structure

MobileNet-Accelerator-RTL/
├── benchmark/                  # Performance measurement tools
├── constraints/                # Synthesis constraints
├── data/                       # Golden reference vectors
├── reports/                    # Post-Synthesis QoR reports
├── rtl/                        # Synthesizable RTL source files
│   ├── thermal/                # Clock gating and thermal management
│   └── (core modules)
├── scripts/                    # Test execution and analysis scripts
├── src/                        # Python golden models and pipelines
├── tb/                         # Verilog Testbenches
├── .gitignore
├── LICENSE
└── README.md

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📄 Acknowledgements

Developed as a submission for the DVCon India 2026 Design Contest. Thanks to the organizers for a challenging and insightful competition.