Download proccedings from DVCon
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Mar 29, 2026 - Shell
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an infrastructure to implement arbitrary indirect registers on top of uvm
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Nov 6, 2017 - SystemVerilog
Sleipnir is a tool for randomizing software data types in python. It is designed to help aid design verification of complex SoC designs. This repo contains the sleipnir tool and a set of examples.
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Feb 19, 2025 - Python
🏆 Top 100 submission for the DVCon India 2026 Design Contest. A highly optimized, Verilog-based MobileNet Accelerator featuring a custom Systolic Array and on-the-fly Global Average Pooling.
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Aug 10, 2026 - Verilog
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