Update concat to immediately concatenate Consts, returning a new Const.

pyrtl/corecircuits.py

@@ -213,6 +213,15 @@ def concat(*args: WireVectorLike) -> WireVector:
 
     arg_wirevectors = tuple(as_wires(arg) for arg in args)
     final_width = sum(len(arg) for arg in arg_wirevectors)
+
+    if all(isinstance(arg, Const) for arg in arg_wirevectors):
+        # If all args are `Const`, do the `concat` now and return the `Const` result.
+        result = 0
+        for const in arg_wirevectors:
+            result = result << const.bitwidth
+            result = result | const.val
+        return Const(result, bitwidth=final_width)
+
     outwire = WireVector(bitwidth=final_width)
     net = LogicNet(op="c", op_param=None, args=arg_wirevectors, dests=(outwire,))
     working_block().add_net(net)
@@ -714,22 +723,27 @@ def match_bitwidth(*args: WireVector, signed: bool = False) -> tuple[WireVector]
 
     Example with sign-extension::
 
-        >>> a = pyrtl.Const(-1, name="a_short", signed=True, bitwidth=2)
-        >>> b = pyrtl.Const(-3, name="b", signed=True, bitwidth=4)
+        >>> a_short = pyrtl.Input(name="a_short", bitwidth=2)
+        >>> b_long = pyrtl.Input(name="b_long", bitwidth=4)
 
-        >>> a, b = pyrtl.match_bitwidth(a, b, signed=True)
-        >>> a.name = "a_long"
-        >>> a.bitwidth, b.bitwidth
-        (4, 4)
+        >>> a_matched = pyrtl.Output(name="a_matched", bitwidth=4)
+        >>> b_matched = pyrtl.Output(name="b_matched", bitwidth=4)
+
+        >>> a, b = pyrtl.match_bitwidth(a_short, b_long, signed=True)
+        >>> a_matched <<= a
+        >>> b_matched <<= b
 
         >>> sim = pyrtl.Simulation()
-        >>> sim.step()
-        >>> bin(sim.inspect("b"))
-        '0b1101'
+        >>> sim.step({"a_short": -1, "b_long": -3})
+
         >>> bin(sim.inspect("a_short"))
         '0b11'
-        >>> bin(sim.inspect("a_long"))
+        >>> bin(sim.inspect("b_long"))
+        '0b1101'
+        >>> bin(sim.inspect("a_matched"))
         '0b1111'
+        >>> bin(sim.inspect("b_matched"))
+        '0b1101'
 
     :param args: :class:`WireVectors<WireVector>` of which to match
         :attr:`~WireVector.bitwidth`

tests/test_analysis.py

@@ -156,34 +156,34 @@ def setUp(self):
 From i
   To o
     Path 0
-      tmp3/3W <-- - -- i/2I, tmp2/2W
-      tmp4/3W <-- | -- tmp1/3W, tmp3/3W
-      o/3O <-- w -- tmp4/3W
+      tmp2/3W <-- - -- i/2I, const_3_1/2C
+      tmp3/3W <-- | -- tmp1/3W, tmp2/3W
+      o/3O <-- w -- tmp3/3W
     Path 1
       tmp0/3W <-- c -- const_0_0/1C, i/2I
       tmp1/3W <-- & -- tmp0/3W, j/3I
-      tmp4/3W <-- | -- tmp1/3W, tmp3/3W
-      o/3O <-- w -- tmp4/3W
+      tmp3/3W <-- | -- tmp1/3W, tmp2/3W
+      o/3O <-- w -- tmp3/3W
   To p
     Path 0
-      tmp5/4W <-- c -- const_3_0/2C, i/2I
-      tmp6/5W <-- - -- k/4I, tmp5/4W
-      p/5O <-- w -- tmp6/5W
+      tmp4/4W <-- c -- const_4_0/2C, i/2I
+      tmp5/5W <-- - -- k/4I, tmp4/4W
+      p/5O <-- w -- tmp5/5W
 From j
   To o
     Path 0
       tmp1/3W <-- & -- tmp0/3W, j/3I
-      tmp4/3W <-- | -- tmp1/3W, tmp3/3W
-      o/3O <-- w -- tmp4/3W
+      tmp3/3W <-- | -- tmp1/3W, tmp2/3W
+      o/3O <-- w -- tmp3/3W
   To p
     (No paths)
 From k
   To o
     (No paths)
   To p
     Path 0
-      tmp6/5W <-- - -- k/4I, tmp5/4W
-      p/5O <-- w -- tmp6/5W
+      tmp5/5W <-- - -- k/4I, tmp4/4W
+      p/5O <-- w -- tmp5/5W
 """
 
 
@@ -382,7 +382,7 @@ def test_pretty_print(self):
         output = io.StringIO()
         paths.print(file=output)
         self.maxDiff = 30000
-        self.assertEqual(output.getvalue(), paths_print_output)
+        self.assertEqual(paths_print_output, output.getvalue())
 
 
 class TestDistance(unittest.TestCase):