Fix an output_to_verilog bug where inlined arithmetic expressions might unintentionaly truncate.

[fdxmw]

In Verilog, the expression a + b in the example below has bitwidth 6:

  input[5:0] a;
  input[5:0] b;
  output[7:0] o;
  assign o = {1'd1, a + b};

This is a major difference from PyRTL, where a + b has bitwidth 7. Assignment to o in this example may trigger a warning, because the concatenation expression has bitwidth 7 (1'd1 has bitwidth 1, a + b has bitwidth 6), while o has bitwidth 8.

Loss of the addition's carry bit can be prevented by explicitly assigning the result to a wider-bitwidth wire:

  wire[6:0] tmp;
  assign tmp = a + b;
  assign o = {1'd1, tmp};

This commit prevents pyrtl.output_to_verilog from inlining arithmetic expressions (+, -, *) to avoid triggering this implicit truncation in Verilog. We can't safely inline these arithmetic expressions because the carry bits may be needed.

We could analyze the GateGraph and check if the carry bits are actually used. For now we keep things simple and never inline arithmetic expressions.

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.
✅ Project coverage is 93.8%. Comparing base (82d8858) to head (0c59ea0).

Additional details and impacted files

@@              Coverage Diff              @@
##           development    #501     +/-   ##
=============================================
+ Coverage         93.8%   93.8%   +0.1%     
=============================================
  Files               30      30             
  Lines             7141    7143      +2     
=============================================
+ Hits              6692    6694      +2     
  Misses             449     449             

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